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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 862 occurrences of 359 keywords
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Results
Found 438 publication records. Showing 438 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
129 | Irith Pomeranz, Sudhakar M. Reddy |
On achieving complete fault coverage for sequential machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3), pp. 378-386, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
103 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara |
A class of sequential circuits with combinational test generation complexity under single-fault assumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 398-403, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault |
84 | Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren |
Quantitative Analysis of In-Field Defects in Image Sensor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 526-534, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
83 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Robust testing for stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 42-46, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models |
81 | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
A Complete Characterization of Path Delay Faults through Stuck-at Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 492-497, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
80 | Michiel M. Ligthart, Rudi J. Stans |
A fault model for PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(2), pp. 265-270, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
76 | Irith Pomeranz, Sudhakar M. Reddy |
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3), pp. 426-432, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
76 | Niraj K. Jha, Qiao Tong |
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 350-354, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
73 | Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck |
Deterministic test generation for non-classical faults on the gate level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 244-251, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST |
72 | Andrej Zemva, Franc Brglez |
Detectable perturbations: a paradigm for technology-specific multi-fault test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 350-357, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system |
72 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Simulating Resistive Bridging and Stuck-At Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1051-1059, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation |
72 | Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen |
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 475-480, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
72 | Feng Shi 0010, Yiorgos Makris |
A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 57-67, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
72 | Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz |
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 178-183, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
68 | Piotr R. Sidorowicz |
Modeling and Testing Transistor Faults in Content-Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 83-90, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
67 | Kent L. Einspahr, Sharad C. Seth |
A switch-level test generation system for synchronous and asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 59-73, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation |
65 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu |
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 64-69, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
65 | Piotr R. Sidorowicz, Janusz A. Brzozowski |
A framework for testing special-purpose memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1459-1468, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
64 | Patrick Kam Lui, Jon C. Muzio |
Constrained parity testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(3), pp. 279-291, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
compaction testing, parity testing, Built-in self-test, signature analysis |
64 | Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 419-424, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
64 | Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu |
Test Generation for Double Stuck-at Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 71-75, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
64 | Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò |
Fault simulation of unconventional faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 677-682, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
61 | Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara |
Compact test generation for bridging faults under IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 310-316, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing |
61 | El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny |
On the generation of test patterns for multiple faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(3), pp. 237-253, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis |
61 | Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty |
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 471-489, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
stuck-at fault diagnosis, Fault simulation |
60 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi |
False-Path Removal Using Delay Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 463-476, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal |
60 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Simulation of at-speed tests for stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 216-220, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test |
60 | Sreejit Chakravarty |
A characterization of robust test-pairs for stuck-open faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(4), pp. 275-286, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
fault simulation, robust tests, stuck-open faults, test generation algorithms |
59 | Alexander Iosupovicz |
Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(5), pp. 452-455, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
fault detection experiments, minimal test set, two-level logic, stuck-at faults, Bridge faults, unate functions |
58 | James Chien-Mo Li |
Diagnosis of single stuck-at faults and multiple timing faults in scan chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 708-718, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
57 | Parag K. Lala, Anup Singh, Alvernon Walker |
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 238-246, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing |
57 | Wuudiann Ke, Premachandran R. Menon |
Multifault and delay-fault testability of multilevel circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(3), pp. 333-336, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testing, testability, delay-faults, multiple stuck-at faults |
57 | Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu |
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3), pp. 362-368, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy |
On Improving Defect Coverage of Stuck-at Fault Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 216-223, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
57 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara |
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 55-62, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure |
56 | Irith Pomeranz, Sudhakar M. Reddy |
Test sequences to achieve high defect coverage for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10), pp. 1017-1029, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
54 | Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya |
Isomorph-Redundancy in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(9), pp. 992-997, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines |
53 | Jan Schat |
Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 235-240, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
53 | Irith Pomeranz, Sudhakar M. Reddy |
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 20-25, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
50 | Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy |
Fsimac: a fault simulator for asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 114-119, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits |
50 | Peter Lidén, Peter Dahlgren |
Switch-level modeling of transistor-level stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 208-215, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling |
50 | Sreejit Chakravarty, Harry B. Hunt III |
On Computing Signal Probability and Detection Probability of Stuck-at Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(11), pp. 1369-1377, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
pseudo gates, logic testing, built-in self test, combinational circuits, random testing, stuck-at faults, combinatorial circuits, testability analysis, detection probability, signal probability, pseudorandom testing, enumeration algorithm |
49 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Simulating Resistive-Bridging and Stuck-At Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2181-2192, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko |
On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 20-24, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
49 | Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs |
Dynamic diagnosis of sequential circuits based on stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 198-203, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm |
49 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Design for high-speed testability of stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 53-56, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay |
49 | Chien-Mo James Li, Edward J. McCluskey |
Diagnosis of Sequence-Dependent Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 187-192, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault |
Use of Fault Dropping for Multiple Fault Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(1), pp. 98-103, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
fault dropping, multiple fault analysis, frontier faults, fault-free circuit, logic testing, stuck at faults, logic circuits, logic circuits, combinatorial circuits, benchmark circuits, gate level, fault collapsing, multiple stuck at faults |
46 | Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara |
Single-control testability of RTL data paths for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 210-215, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test |
46 | Irith Pomeranz, Sudhakar M. Reddy |
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 412-417, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
test generation, fault simulation, stuck-at faults, bridging faults, circuit partitioning |
46 | Janusz A. Brzozowski, Kaamran Raahemifar |
Testing C-elements is not elementary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 150-159, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence |
46 | Fatih Kocan, Daniel G. Saab |
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 405-420, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Dynamic fault diagnosis, FPGA, Emulation, Stuck-at faults, Circuits, Gate-level |
46 | Amy Streich, Alex Kondratyev, Lief Sorensen |
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 171-180, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ATPG, asynchronous circuits, stuck-at faults, partial scan |
46 | Michael J. Liebelt, Cheng-Chew Lim |
A method for determining whether asynchronous circuits are self-checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 472-477, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise |
46 | Charles E. Stroud, Ahmed E. Barbour |
Testability and test generation for majority voting fault-tolerant circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(3), pp. 201-214, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults |
46 | Irith Pomeranz, W. Kent Fuchs |
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 486-491, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
46 | Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu |
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 216-221, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Peter A. Krauss, Andreas Ganz, Kurt Antreich |
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(3), pp. 227-245, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fault parallelism, search space parallelism, sequential circuits, ATPG |
45 | Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman |
Diagnostic simulation of stuck-at faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 87-97, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
diagnostic power, diagnostic simulation, diagnosis, equivalence classes, diagnostic resolution |
45 | Sandip Kundu, Sudhakar M. Reddy |
Robust tests for parity trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(3), pp. 191-200, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
linear gates, parity trees, URTS, robust tests, test length |
45 | Osman Hasan, Naeem Abbasi, Sofiène Tahar |
Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, 7th International Conference, IFM 2009, Düsseldorf, Germany, February 16-19, 2009. Proceedings, pp. 277-291, 2009, Springer, 978-3-642-00254-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
45 | Wen-Ben Jone, Patrick H. Madden |
Multiple fault testing using minimal single fault test set for fanout-free circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 149-157, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
44 | Irith Pomeranz, Sudhakar M. Reddy |
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May 1998, Princeton, NJ, USA, pp. 289-295, 1998, IEEE Computer Society, 0-8186-8436-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
42 | Jack R. Smith, Tian Xia, Charles E. Stroud |
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(3), pp. 239-253, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
stuck-at faults, bridging faults, delay faults |
42 | Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui |
On Variable-Shift-Based Fault Compensation of Fuzzy Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 436-444, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fault compensation, fault tolerance, fuzzy control, stuck-at faults, on-line testing |
42 | Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham |
A novel test generation approach for parametric faults in linear analog circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 470-475, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits |
42 | Irith Pomeranz, Sudhakar M. Reddy |
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5), pp. 589-600, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
42 | Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz |
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 317-324, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy |
Scan BIST Targeting Transition Faults Using a Markov Source. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 497-502, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik |
A BIST scheme for the detection of path-delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 422-431, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
42 | Zhigang Jiang, Sandeep K. Gupta 0001 |
Threshold testing: Covering bridging and other realistic faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 390-397, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana |
Faulty behavior of storage elements and its effects on sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 446-452, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
41 | Ralf Eickhoff, Ulrich Rückert 0001 |
Tolerance of Radial Basis Functions Against Stuck-At-Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (2) ![In: Artificial Neural Networks: Formal Models and Their Applications - ICANN 2005, 15th International Conference, Warsaw, Poland, September 11-15, 2005, Proceedings, Part II, pp. 1003-1008, 2005, Springer, 3-540-28755-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir |
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(9), pp. 1289-1294, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu |
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 222-227, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
Multiple Faults: Modeling, Simulation and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 592-597, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ATPG Modeling, Fault Modeling, Multiple Fault |
41 | Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin |
Redundancy Identification Using Transitive Closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 4-9, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
38 | Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel |
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(12), pp. 1646-1651, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Space compaction, testing, stuck-at faults, system-on-a-chip |
38 | Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri |
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 62-72, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits |
38 | Takehiro Ito, Itsuo Takanami |
On fault injection approaches for fault tolerance of feedforward neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 88-93, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
snapping faults, learning cycle, ditribution of correlations, output neuron, fault tolerance, reliabilities, fault injection, stuck-at faults, computer simulation, learning algorithm, feedforward neural networks, feedforward neural nets, recognition rate, learning methods, internal structure |
38 | Joakim Aidemark, Peter Folkesson, Johan Karlsson |
On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 68-74, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu |
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 16-18 December 2002, Tsukuba-City, Ibarski, Japan, pp. 275-282, 2002, IEEE Computer Society, 0-7695-1852-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Irith Pomeranz, Sudhakar M. Reddy |
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1074-1083, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Manan Syal, Michael S. Hsiao, Sreejit Chakravarty |
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1034-1043, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Irith Pomeranz, Sudhakar M. Reddy |
The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 215-220, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Sumit Ghosh, Tapan J. Chakraborty |
On behavior fault modeling for digital designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(2), pp. 135-151, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model |
38 | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
A synthesis and optimization procedure for fully and easily testable sequential machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10), pp. 1100-1107, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
38 | Jia Di, Parag K. Lala, Dilip P. Vasudevan |
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 371-379, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Srikanth Venkataraman, W. Kent Fuchs |
Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 381-387, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu |
On the fault diagnosis in the presence of unknown fault models using pass/fail information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2987-2990, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Leendert M. Huisman |
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 91-101, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Wuudiann Ke, Premachandran R. Menon |
Multifault testability of delay-testable circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 400-409, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits |
38 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
SWiTEST: a switch level test generation system for CMOS combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5), pp. 625-637, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
35 | Navya Mohan, J. P. Anita |
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 83, pp. 24-32, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
35 | Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita |
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019, pp. 284-290, 2019, IEEE, 978-1-7281-0392-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
35 | Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita |
An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3), pp. 1063-1074, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
35 | Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy |
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2018, Harbin, China, August 15-17, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-5180-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
35 | Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita |
Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
35 | Cheng-Hung Wu, Kuen-Jong Lee |
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, pp. 306-311, 2014, IEEE Computer Society, 978-1-4799-6030-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
35 | Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi |
Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, pp. 114-119, 2011, IEEE Computer Society, 978-1-4577-1984-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
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