Search results for "stuck-at-faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
129	Irith Pomeranz, Sudhakar M. Reddy	On achieving complete fault coverage for sequential machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
103	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
84	Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren	Quantitative Analysis of In-Field Defects in Image Sensor Arrays.	DFT	2007	DBLP DOI BibTeX RDF
83	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
81	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
80	Michiel M. Ligthart, Rudi J. Stans	A fault model for PLAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
76	Irith Pomeranz, Sudhakar M. Reddy	Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
76	Niraj K. Jha, Qiao Tong	Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring.	EURO-DAC	1990	DBLP DOI BibTeX RDF
73	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
72	Andrej Zemva, Franc Brglez	Detectable perturbations: a paradigm for technology-specific multi-fault test generation.	VTS	1995	DBLP DOI BibTeX RDF	detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
72	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001	Simulating Resistive Bridging and Stuck-At Faults.	ITC	2003	DBLP DOI BibTeX RDF	Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation
72	Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen	Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
72	Feng Shi 0010, Yiorgos Makris	A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
72	Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
68	Piotr R. Sidorowicz	Modeling and Testing Transistor Faults in Content-Addressable Memories.	MTDT	1999	DBLP DOI BibTeX RDF
67	Kent L. Einspahr, Sharad C. Seth	A switch-level test generation system for synchronous and asynchronous circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
65	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu	A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations.	VTS	1999	DBLP DOI BibTeX RDF
65	Piotr R. Sidorowicz, Janusz A. Brzozowski	A framework for testing special-purpose memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
64	Patrick Kam Lui, Jon C. Muzio	Constrained parity testing.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	compaction testing, parity testing, Built-in self-test, signature analysis
64	Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.	VLSI Design	2006	DBLP DOI BibTeX RDF
64	Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu	Test Generation for Double Stuck-at Faults.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
64	Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò	Fault simulation of unconventional faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
61	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
61	El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny	On the generation of test patterns for multiple faults.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis
61	Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty	Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	stuck-at fault diagnosis, Fault simulation
60	Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi	False-Path Removal Using Delay Fault Simulation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal
60	Tapan J. Chakraborty, Vishwani D. Agrawal	Simulation of at-speed tests for stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
60	Sreejit Chakravarty	A characterization of robust test-pairs for stuck-open faults.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	fault simulation, robust tests, stuck-open faults, test generation algorithms
59	Alexander Iosupovicz	Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	fault detection experiments, minimal test set, two-level logic, stuck-at faults, Bridge faults, unate functions
58	James Chien-Mo Li	Diagnosis of single stuck-at faults and multiple timing faults in scan chains.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
57	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
57	Wuudiann Ke, Premachandran R. Menon	Multifault and delay-fault testability of multilevel circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testing, testability, delay-faults, multiple stuck-at faults
57	Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu	On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
57	Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy	On Improving Defect Coverage of Stuck-at Fault Tests.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
57	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure
56	Irith Pomeranz, Sudhakar M. Reddy	Test sequences to achieve high defect coverage for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
54	Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya	Isomorph-Redundancy in Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines
53	Jan Schat	Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns.	DDECS	2008	DBLP DOI BibTeX RDF
53	Irith Pomeranz, Sudhakar M. Reddy	On Generating Test Sets that Remain Valid in the Presence of Undetected Faults.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
50	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
50	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
50	Sreejit Chakravarty, Harry B. Hunt III	On Computing Signal Probability and Detection Probability of Stuck-at Faults.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	pseudo gates, logic testing, built-in self test, combinational circuits, random testing, stuck-at faults, combinatorial circuits, testability analysis, detection probability, signal probability, pseudorandom testing, enumeration algorithm
49	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001	Simulating Resistive-Bridging and Stuck-At Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
49	Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko	On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
49	Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs	Dynamic diagnosis of sequential circuits based on stuck-at faults.	VTS	1996	DBLP DOI BibTeX RDF	dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm
49	Tapan J. Chakraborty, Vishwani D. Agrawal	Design for high-speed testability of stuck-at faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
49	Chien-Mo James Li, Edward J. McCluskey	Diagnosis of Sequence-Dependent Chips.	VTS	2002	DBLP DOI BibTeX RDF
46	Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault	Use of Fault Dropping for Multiple Fault Analysis.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	fault dropping, multiple fault analysis, frontier faults, fault-free circuit, logic testing, stuck at faults, logic circuits, logic circuits, combinatorial circuits, benchmark circuits, gate level, fault collapsing, multiple stuck at faults
46	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
46	Irith Pomeranz, Sudhakar M. Reddy	Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	test generation, fault simulation, stuck-at faults, bridging faults, circuit partitioning
46	Janusz A. Brzozowski, Kaamran Raahemifar	Testing C-elements is not elementary.	ASYNC	1995	DBLP DOI BibTeX RDF	C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence
46	Fatih Kocan, Daniel G. Saab	Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Dynamic fault diagnosis, FPGA, Emulation, Stuck-at faults, Circuits, Gate-level
46	Amy Streich, Alex Kondratyev, Lief Sorensen	Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach.	ASYNC	2002	DBLP DOI BibTeX RDF	ATPG, asynchronous circuits, stuck-at faults, partial scan
46	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
46	Charles E. Stroud, Ahmed E. Barbour	Testability and test generation for majority voting fault-tolerant circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults
46	Irith Pomeranz, W. Kent Fuchs	A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
46	Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu	Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
45	Peter A. Krauss, Andreas Ganz, Kurt Antreich	Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	fault parallelism, search space parallelism, sequential circuits, ATPG
45	Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman	Diagnostic simulation of stuck-at faults in combinational circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	diagnostic power, diagnostic simulation, diagnosis, equivalence classes, diagnostic resolution
45	Sandip Kundu, Sudhakar M. Reddy	Robust tests for parity trees.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	linear gates, parity trees, URTS, robust tests, test length
45	Osman Hasan, Naeem Abbasi, Sofiène Tahar	Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays.	IFM	2009	DBLP DOI BibTeX RDF
45	Wen-Ben Jone, Patrick H. Madden	Multiple fault testing using minimal single fault test set for fanout-free circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
44	Irith Pomeranz, Sudhakar M. Reddy	Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage.	VTS	1998	DBLP DOI BibTeX RDF
42	Jack R. Smith, Tian Xia, Charles E. Stroud	An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	stuck-at faults, bridging faults, delay faults
42	Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui	On Variable-Shift-Based Fault Compensation of Fuzzy Controllers.	DFT	2001	DBLP DOI BibTeX RDF	fault compensation, fault tolerance, fuzzy control, stuck-at faults, on-line testing
42	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
42	Irith Pomeranz, Sudhakar M. Reddy	A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
42	Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.	ICCD	2007	DBLP DOI BibTeX RDF
42	Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy	Scan BIST Targeting Transition Faults Using a Markov Source.	ISQED	2004	DBLP DOI BibTeX RDF
42	Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik	A BIST scheme for the detection of path-delay faults.	ITC	1998	DBLP DOI BibTeX RDF
42	Zhigang Jiang, Sandeep K. Gupta 0001	Threshold testing: Covering bridging and other realistic faults.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
42	W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana	Faulty behavior of storage elements and its effects on sequential circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
41	Ralf Eickhoff, Ulrich Rückert 0001	Tolerance of Radial Basis Functions Against Stuck-At-Faults.	ICANN (2)	2005	DBLP DOI BibTeX RDF
41	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
41	Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu	Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
41	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Multiple Faults: Modeling, Simulation and Test.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	ATPG Modeling, Fault Modeling, Multiple Fault
41	Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin	Redundancy Identification Using Transitive Closure.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
38	Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel	Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Space compaction, testing, stuck-at faults, system-on-a-chip
38	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
38	Takehiro Ito, Itsuo Takanami	On fault injection approaches for fault tolerance of feedforward neural networks.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	snapping faults, learning cycle, ditribution of correlations, output neuron, fault tolerance, reliabilities, fault injection, stuck-at faults, computer simulation, learning algorithm, feedforward neural networks, feedforward neural nets, recognition rate, learning methods, internal structure
38	Joakim Aidemark, Peter Folkesson, Johan Karlsson	On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy.	IOLTS	2003	DBLP DOI BibTeX RDF
38	Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu	An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.	PRDC	2002	DBLP DOI BibTeX RDF
38	Irith Pomeranz, Sudhakar M. Reddy	A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.	ITC	1998	DBLP DOI BibTeX RDF
38	Manan Syal, Michael S. Hsiao, Sreejit Chakravarty	Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.	ITC	2004	DBLP DOI BibTeX RDF
38	Irith Pomeranz, Sudhakar M. Reddy	The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality.	VLSI Design	2009	DBLP DOI BibTeX RDF
38	Sumit Ghosh, Tapan J. Chakraborty	On behavior fault modeling for digital designs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model
38	Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	A synthesis and optimization procedure for fully and easily testable sequential machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
38	Jia Di, Parag K. Lala, Dilip P. Vasudevan	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.	DFT	2005	DBLP DOI BibTeX RDF
38	Srikanth Venkataraman, W. Kent Fuchs	Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
38	T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu	On the fault diagnosis in the presence of unknown fault models using pass/fail information.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
38	Leendert M. Huisman	Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
38	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
38	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
35	Navya Mohan, J. P. Anita	Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults.	Integr.	2022	DBLP DOI BibTeX RDF
35	Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita	Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults.	ISQED	2019	DBLP DOI BibTeX RDF
35	Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita	An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
35	Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy	Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run.	ITC-Asia	2018	DBLP DOI BibTeX RDF
35	Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita	Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults.	ISCAS	2017	DBLP DOI BibTeX RDF
35	Cheng-Hung Wu, Kuen-Jong Lee	An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults.	ATS	2014	DBLP DOI BibTeX RDF
35	Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi	Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF