Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Henning Gundersen, Yngvar Berg	A novel ternary more, less and equality circuit using recharged semi-floating gate devices.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Nima Maghari, Omid Shoaei	A dynamic start-up circuit for low voltage CMOS current mirrors with power-down support.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
22	Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang	On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
22	Raoul F. Badaoui, Ranga Vemuri	Analog VLSI circuit-level synthesis using multi-placement structures.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
22	Yehya H. Ghallab, Wael M. Badawy, Karan V. I. S. Kaler	A Novel PH Sensor Using Differential ISFET Current Mode Read-Out Circuit.	ICMENS	2003	DBLP DOI BibTeX RDF	Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits
22	Faizal Arya Samman, Rhiza S. Sadjad, Eniman Y. Syamsuddin	The reconfigurable membership function circuit using analog bipolar electronics.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
22	C.-J. Richard Shi, Sheldon X.-D. Tan	Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
22	D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama	Correlation method of circuit-performance and technology fluctuations for improved design reliability.	ASP-DAC	2001	DBLP DOI BibTeX RDF
22	Forrest H. Bennett III, John R. Koza, Jessen Yu, William Mydlowec	Automatic Synthesis, Placement, and Routing of an Amplifier Circuit by Means of Genetic Programming.	ICES	2000	DBLP DOI BibTeX RDF
22	Vesselin K. Vassilev, Julian F. Miller	Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
22	Christoph Maier, Markus Emmenegger, Stefano Taschini, Henry Baltes, Jan G. Korvink	Equivalent circuit model of resistive IC sensors derived with the box integration method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
22	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.	ISMVL	1999	DBLP DOI BibTeX RDF
22	Abhijit Dharchoudhury, Sung-Mo Kang	Worst-case analysis and optimization of VLSI circuit performances.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
22	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Circuit structure relations to redundancy and delay.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Fadi Y. Busaba, Parag K. Lala	Self-checking combinational circuit design for single and unidirectional multibit error.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Input encoding, output encoding, unidirectional error, self-checking
22	Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang 0001	Algorithms for transient three-dimensional mixed-level circuit and device simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
22	Yung-Ho Shih, Sung-Mo Kang	Analytic transient solution of general MOS circuit primitives.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
22	Evangelos Simoudis	A knowledge-based system for the evaluation and redesign of digital circuit networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija	Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design.	PATMOS	2006	DBLP DOI BibTeX RDF
22	Ramamohan Paturi, Pavel Pudlák	On the complexity of circuit satisfiability.	STOC	2010	DBLP DOI BibTeX RDF	NP-completeness, circuit satisfiability
22	Zhihong Feng, Zhigui Lin, Wei Fang, Wei Wang, Zhitao Xiao	Analog Circuit Fault Fusion Diagnosis Method Based on Support Vector Machine.	ISNN (2)	2009	DBLP DOI BibTeX RDF	Multi- classification, Support Vector Machine, Fault diagnosis, Analog circuit
22	Nitin Saxena 0001	Diagonal Circuit Identity Testing and Lower Bounds.	ICALP (1)	2008	DBLP DOI BibTeX RDF	identity testing, depth 3, depth 4, lower bounds, determinant, arithmetic circuit, permanent
22	Alexander Khitun, Mingqiang Bao, Yina Wu, Ji-Young Kim, Augustin Hong, Ajey P. Jacob, Kosmas Galatsis, Kang L. Wang	Spin Wave Logic Circuit on Silicon Platform.	ITNG	2008	DBLP DOI BibTeX RDF	nanoscale architectures, logic circuit, spin waves
22	Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk	High-Quality Circuit Synthesis for Modern Technologies.	ISQED	2008	DBLP DOI BibTeX RDF	nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis
22	Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung	A hybridized genetic parallel programming based logic circuit synthesizer.	GECCO	2006	DBLP DOI BibTeX RDF	FlowMap, a hybridized genetic parallel programming logic circuit synthesizer, genetic parallel programming, field programmable gate array, technology mapping, LookUp table
22	Dana Angluin, James Aspnes, Jiang Chen, Yinghua Wu	Learning a circuit by injecting values.	STOC	2006	DBLP DOI BibTeX RDF	learning, circuit, gene regulatory network
22	Yuh-Ren Tsai, Che-Wei Lo	Banyan-based Architecture for Quasi-Circuit Switching.	ICNS	2006	DBLP DOI BibTeX RDF	Birkhoff-von Neumann Switches, Quasi-circuit Switching, Multi-stage Switches, Packet Delay Control, Quality of Services
22	Henry H. Y. Chan, Zeljko Zilic	Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization.	ISQED	2005	DBLP DOI BibTeX RDF	Analog circuit optimization, adjoint analysis, sensitivity analysis, parasitic extraction
22	Hovhannes Avoyan, Barry Levine	Web engineering with the visual software circuit board.	WWW (Alternate Track Papers & Posters)	2004	DBLP DOI BibTeX RDF	circuit based software development, visual programming, web engineering, component based development, web application development, rapid application development
22	Abdellah Idrissi, Ahlem Ben Hassine	Circuit Consistencies.	PRICAI	2004	DBLP DOI BibTeX RDF	Circuit Consistency, Constraint Satisfaction
22	Baohua Wang, Pinaki Mazumder	On optimality of adiabatic switching in MOS energy-recovery circuit.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuit, power clock optimization, variational calculus
22	Baohua Wang, Pinaki Mazumder	On optimality of adiabatic switching in MOS energy-recovery circuit.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuit, power clock optimization, variational calculus
22	Lech Józwiak	Advanced AI Search Techniques in Modern Digital Circuit Synthesis.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	automated design problem solving, double-beam search, genetic engineering algorithm, quick scan, artificial intelligence, heuristic search, circuit synthesis
22	Valentine Kabanets, Russell Impagliazzo	Derandomizing polynomial identity tests means proving circuit lower bounds.	STOC	2003	DBLP DOI BibTeX RDF	BPP, NEXP, circuit lower bounds, derandomization, polynomial identity testing
22	Larry J. Stockmeyer, Albert R. Meyer	Cosmological lower bound on the circuit complexity of a small problem in logic.	J. ACM	2002	DBLP DOI BibTeX RDF	WS1S, practical undecidability, computational complexity, lower bound, logic, Circuit complexity, decision problem
22	Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee	Analog circuit equivalent faults in the D.C. domain.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits
22	Ke Yang	Integer Circuit Evaluation is PSPACE-Complete.	CCC	2000	DBLP DOI BibTeX RDF	Integer Circuit, Chinese Remainder Theorem, PSPACE
22	Sadiq M. Sait, Habib Youssef, Munir M. Zahra	Tabu Search Based Circuit Optimization.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	CMOS/BiCMOS, Mixed Technologies, Tabu Search, Search Algorithms, Critical Path, False Path, Circuit Optimization
22	Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka	Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	hierarchical fault tracing, electron beam testing, hierarchically structured CAD layout, successive circuit extraction
22	Charles J. DeVane	Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	cycle simulation, levelized compiled code, logic simulation, circuit partitioning
22	Santonu Sarkar, Anupam Basu, Arun K. Majumdar	Analyzing Controllability of a Hardware Circuit for its Reuse.	VLSI Design	1997	DBLP DOI BibTeX RDF	hardware circuit controllability, external controllability, FSM model, finite state machines, finite state machine model
21	Jun Liu 0046, Ming-xin Yang, Jian-Bo Wang	Thick Film Integrated Circuit Design of Multi-measurement Module.	APWCS	2010	DBLP DOI BibTeX RDF	Thick film integrated circuit, Signal adjustment circuit, Thermocouple, Spi, Calibration
21	Huang Yushui, Zhu Ling, Xin Yugang	Analysis and Optimization Design of M57959L Module-Based IGBT Drive Circuit.	APWCS	2010	DBLP DOI BibTeX RDF	IGBT, drive circuit, M57959L, optimization circuit, High reliability
21	Shinichi Tamura, Yuko Mizuno-Matsumoto, Yen-Wei Chen 0001, Kazuki Nakamura	Association and Abstraction on Neural Circuit Loop and Coding.	IIH-MSP	2009	DBLP DOI BibTeX RDF	Brain information processing, Neuron circuit, Loop circuit, Associative memory
21	M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor	Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential circuit TPG, back-jumping, conflict-directed backtrack, three-state (tri-state) circuit TPG, ATPG, cost estimates
21	Kanad Chakraborty, Pinaki Mazumder	An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards.	ICCAD	1996	DBLP DOI BibTeX RDF	bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing
21	Anne E. Gattiker, Wojciech Maly	Current signatures [VLSI circuit testing].	VTS	1996	DBLP DOI BibTeX RDF	VLSI circuit testing, current signature, passive defects, active defects, VLSI, integrated circuit testing, CMOS integrated circuits, I/sub DDQ/ testing
21	Tan-Li Chou, Kaushik Roy 0001	Estimation of sequential circuit activity considering spatial and temporal correlations.	ICCD	1995	DBLP DOI BibTeX RDF	sequential circuit activity estimation, signal activity, internal nodes, sequential logic circuits, logic signals, ESTG, extended state transition graph, exact signal probabilities, large circuits, state logic, logic simulation results, graph theory, finite state machines, finite state machine, sequential circuits, spatial correlations, circuit switching, switching activities, approximate method, temporal correlations
21	Michael Goedecke, Sorin A. Huss, Kai Morich	Automatic Parallelization of the Visual Data-Flow Language Cantata for Efficient Characterization of Analog Circuit Behavior.	VL	1995	DBLP DOI BibTeX RDF	engineering workstations, Cantata visual data-flow language, analog circuit behavior characterisation, application specific functions, execution time reduction, data-flow scheduler, usable workstations, usable workstation performance, program availability, fully automated process, simulation, computational complexity, load balancing, parallel programming, resource allocation, visual languages, digital simulation, processor scheduling, circuit analysis computing, workloads, automatic parallelization, parallel languages, distributed environment, workstations, analogue circuits, control operators
21	Harry Hengster, Rolf Drechsler, Bernd Becker 0001	On the application of local circuit transformations with special emphasis on path delay fault testability.	VTS	1995	DBLP DOI BibTeX RDF	local circuit transformations, path delay fault testability, SALT, logic testing, delays, integrated circuit testing, automatic testing
21	Khaled Saab 0001, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski	Frequency-based BIST for analog circuit testin.	VTS	1995	DBLP DOI BibTeX RDF	waveform generators, frequency-based BIST, analog circuit testing, sine wave generator, sinusoidal input signals, variable frequency input stimulus, frequency input signal, T-BIST approach, frequency-counter BIST approach, VLSI, VLSI, built-in self test, integrated circuit testing, analogue integrated circuits
21	Shyue-Win Wei	A Systolic Power-Sum Circuit for GF(2^m).	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	systolic power-sum circuit, power-sum circuit, error correction codes, error-correcting codes, finite field, systolic arrays, decoding, logic circuits, logic gates, logical gates
21	Baruch Awerbuch, Rainer Gawlick, Frank Thomson Leighton, Yuval Rabani	On-line Admission Control and Circuit Routing for High Performance Computing and Communication	FOCS	1994	DBLP DOI BibTeX RDF	greedy-based approaches, on-line admission control, circuit routing, high performance communication, virtual circuit routing, real-lime database servers, lower bounds, high performance computing, hypercubes, trees, upper bounds, optimal algorithms, arrays, video-servers
21	Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza	A Systolic Redundant Residue Arithmetic Error Correction Circuit.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	systolic redundant residue arithmetic error correction circuit, concurrent fault tolerance capability, redundant residue number system, high speed VLSI circuit realization, parallel systolic architecture, parallel algorithms, VLSI, systolic arrays, digital arithmetic, error correction, real-time applications, error recovery, decision table, processing element, transient errors, residue arithmetic, memory element
21	Andrew Chi-Chih Yao	Quantum Circuit Complexity	FOCS	1993	DBLP DOI BibTeX RDF	quantum communication complexity, quantum circuit complexity, Boolean circuit model, quantum Turing machine, polynomial time
21	Jeff Edmonds, Steven Rudich, Russell Impagliazzo, Jirí Sgall	Communication Complexity Towards Lower Bounds on Circuit Depth	FOCS	1991	DBLP DOI BibTeX RDF	almost optimal lower bound, circuit depth, circuit depth complexity, n-bit Boolean function, communication game characterization, universal composition relation, lower bounds
21	Sampath Rangarajan, Donald S. Fussell, Miroslaw Malek	Built-In Testing of Integrated Circuit Wafers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	integrated circuit wafers, silicon wafers, VLSI, integrated circuit testing, automatic testing, built-in testing, production testing
21	P. Sadayappan, V. Visvanathan	Circuit Simulation on Shared-Memory Multiprocessors.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	vector multiprocessor, sparse matrix solution, parallel processing, parallelization, shared-memory multiprocessors, digital simulation, circuit CAD, circuit simulator, parallel implementation
21	Peter Muth	A Nine-Valued Circuit Model for Test Generation.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	many-valued model, single and multiple faults, test generation, diagnosis, sequential circuit, Circuit testing, D-algorithm
21	Yinghai Lu, Li Shang, Hai Zhou 0001, Hengliang Zhu, Fan Yang 0001, Xuan Zeng 0001	Statistical reliability analysis under process variation and aging effects.	DAC	2009	DBLP DOI BibTeX RDF	process variations, yield, NBTI
21	Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song	Transforming Cyclic Circuits Into Acyclic Equivalents.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
21	Sudhakar M. Reddy, Irith Pomeranz, Chen Liu	On tests to detect via opens in digital CMOS circuits.	DAC	2008	DBLP DOI BibTeX RDF	constrained stuck-at tests, test generation, DFT, open defects
21	David T. Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt	Single event transients in combinatorial circuits.	SBCCI	2005	DBLP DOI BibTeX RDF	soft errors, integrated circuits, single event transients
21	Volkan Kursun, Eby G. Friedman	Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
21	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
21	Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan	VERILAT: verification using logic augmentation and transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
21	Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
21	Sandeep N. Bhatt, Gianfranco Bilardi, Geppino Pucci	Area-Universal Circuits with Constant Slowdown.	ARVLSI	1999	DBLP DOI BibTeX RDF
21	M. Hira, Dipankar Sarkar 0001	Verification of Tempura specification of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
21	Tadahiro Kuroda, Takayasu Sakurai	Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
21	Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison	On properties of algebraic transformations and the synthesis of multifault-irredundant circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
21	Bruce G. Lindsay 0001, Laura M. Haas, C. Mohan 0001, Paul F. Wilms, Robert A. Yost	Computation & Communication in R*: A Distributed Database Manager (Extended Abstract). (long version: ACM Trans. Comput. Syst. 2(1): 24-38(1984))	SOSP	1983	DBLP DOI BibTeX RDF
21	Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa	High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.	PATMOS	2006	DBLP DOI BibTeX RDF
21	Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard	Speed Indicators for Circuit Optimization.	PATMOS	2005	DBLP DOI BibTeX RDF
21	Roshan Weerasekera, Li-Rong Zheng 0001, Dinesh Pamunuwa, Hannu Tenhunen	Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses.	PATMOS	2005	DBLP DOI BibTeX RDF
21	Nadia Nedjah, Luiza de Macedo Mourelle	A Comparison of Two Circuit Representations for Evolutionary Digital Circuit Design.	IEA/AIE	2004	DBLP DOI BibTeX RDF
21	Razvan Ionita, Andrei Vladimirescu, Paul G. A. Jespers	Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.	PATMOS	2002	DBLP DOI BibTeX RDF
21	Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi	Hierarchical approach to exact symbolic analysis of large analog circuits.	DAC	2004	DBLP DOI BibTeX RDF	MEMS and/or RF design tools, behavioral modeling, analog, circuit simulation, symbolic analysis, mixed-signal
21	Roland W. Freund, Peter Feldmann	Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation.	DATE	1998	DBLP DOI BibTeX RDF	linear passive multi-terminal circuit, matrix-Pade approximants, Lanczos-type process, interconnect analysis, simulation, synthesis, transfer function
21	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga	A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	marginal delay, test generation, combinational circuit, gate delay faults
21	Michael G. McNamer, H. Troy Nagle	ITA: An algorithm for IDDQ testability analysis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	integrated circuit testing, testability analysis, I DDQ testing, leakage faults
21	Sandeep Pagey	Fast functional testing of delay-insensitive circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates
20	Eduardo José Solteiro Pires, Luís Mendes, Paulo B. de Moura Oliveira, José António Tenreiro Machado, João Caldinhas Vaz, Maria João Rosário	Design of Radio-Frequency Integrated CMOS Discrete Tuning Varactors Using the Particle Swarm Optimization Algorithm.	IWANN (2)	2009	DBLP DOI BibTeX RDF	automated circuit synthesis and radio-frequency integrated circuits, Particle swarm optimization, analog circuit design
20	Yan Sun, Xin Zhang, Xi Jin	High-Performance Carry Select Adder Using Fast All-One Finding Logic.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	fast all-one finding circuit, add-one circuit, carry-select adder
20	Hiroki Morizumi, Jun Tarui	Linear-Size Log-Depth Negation-Limited Inverter for k -Tonic Binary Sequences.	TAMC	2007	DBLP DOI BibTeX RDF	negation-limited circuit, k-tonic, circuit complexity, inverter
20	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Safe Delay Optimization for Physical Synthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
20	Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel	Data structures and algorithms for simplifying reversible circuits.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Circuit simplification, circuit libraries, optimal subcircuit
20	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	Yield-Driven, False-Path-Aware Clock Skew Scheduling.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	performance-related circuit yield loss, circuit-level parameters, DFM, clock skew scheduling
20	Paul F. Stelling, Vojin G. Oklobdzija	Implementing Multiply-Accumulate Operation in Multiplication Time.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed
20	Po-Ching Hsu, Sying-Jyan Wang	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
20	Fidel Muradali, Janusz Rajski	A self-driven test structure for pseudorandom testing of non-scan sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
20	Nur A. Touba, Edward J. McCluskey	Test point insertion based on path tracing.	VTS	1996	DBLP DOI BibTeX RDF	probabilistic techniques, primary inputs, insertion methods, VLSI, VLSI, fault diagnosis, logic testing, logic testing, probability, built-in self test, timing, integrated circuit testing, BIST, automatic testing, fault coverage, test point insertion, path tracing, circuit-under-test
20	Karim Arabi, Bozena Kaminska	Oscillation-test strategy for analog and mixed-signal integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs
20	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
20	Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering	Self timed division and square-root extraction.	VLSI Design	1996	DBLP DOI BibTeX RDF	self-timed integrated circuit, square-root extraction, mathematical algorithm, logic level, binary notation, iterative methods, design methodology, integrated circuit design, division, dividing circuits, quotient, pipeline arithmetic, pipelined arithmetic, functional blocks
20	Bradley C. Kuszmaul	The RACE network architecture.	IPPS	1995	DBLP DOI BibTeX RDF	RACE network architecture, high-performance parallel interconnection network, 6-port switches, preemptable circuit switched strategy, self-regulating circuit, output delay, performance evaluation, real-time systems, parallel architectures, mesh, real-time constraints, Clos network, fat-tree, parallel computer system
20	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
20	Anirudh Devgan	Accurate device modeling techniques for efficient timing simulation of integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models
20	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area