Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link
25	Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi	A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang	A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	P.-F. Rüedi, R. Quaglia, H.-R. Graf	A 90 μW at 1 fps and 1.33 mW at 30 fps 120 dB intra-scene dynamic range 640 × 480 stacked image sensor for autonomous vision systems.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Nick Zhang, Young Suk Kim, Peter Hsu, Samsoo Kim, Derek Tao, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li, Tsung-Yung Jonathan Chang	A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kihwang Son, Seulki Park, Kyunghoon Jung, Jun-Gyu Kim, Younggun Ko, Keonyong Cheon, Changkeun Yoon, Jiho Kim, Jaehun Jeong, Taehun Myung, Changmin Hong, Weonwi Jang, Min-Chul Sun, Sungil Jo, Ju-Youn Kim, Byungmoo Song, Yuri Yasuda-Masuoka, Ja-Hum Ku, Gitae Jeong	Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Seongjae Heo, Dongmin Kim, Wooseok Choi, Sanghyun Ban, Ohhyuk Kwon, Hyunsang Hwang	Experimental Demonstration of Probabilistic-Bit (p-bit) Utilizing Stochastic Oscillation of Threshold Switch Device.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew, A. Chatterjee, B. Chauhan, N. Dandeti, J. Desai, M. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack, Y. Greenzweig, J. Giacobbe, Walid M. Hafez, E. Haralson, A. Hegde, A. Illa, M. Islam, S. Jain, M. Jang, J. Nguyen, T. Tong, L. Jiang, Eric Karl, P. Kalangi, G. Khoo, A. Krishnamoorthy, B. Kuns, W. Li, R. Livengood, T. Malik, R. Priyanka, H. Faraby, Y. Maymon, K. Mistry, K. Morgan, S. Natarajan, O. Nevo, M. Oh, P. Pardy, J. Park, P. Penmatsa, B. Phelps, C. Peterson, S. Rajappa, A. Raveh, A Rezaie, T. Ravishankar, R. Ramaswamy, S. Reddy, R. Saha, S. Sen, R. Sanchez, R. Sanaga, B. Simkhovich, Bernhard Sell, M. Senger, B. Schnarch, M. Seshadri, O. Sidorov, S. Subramanian, K. Subramanian, B. Truong, S. Bangalore, Jeffery Hicks, S. Venkatesh, D. Christensen, K. Bhargav, M. Von Haartman, P. Joshi, S. Zickel, C.-H. Lin, J. Huening, T.-H. Wu, N. Bakken, A. Afzal, A. Raman, Sj. Rao, V. Kawar, J. Neirynck, D. Bradley, M. Duwe, S. Wu, V. Patil, M. Bayoumy	E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hisashi Inoue, Hiroto Tamura, Ai Kitoh, Xiangyu Chen, Zolboo Byambadorj, Takeaki Yajima, Yasushi Hotta, Tetsuya Iizuka, Gouhei Tanaka, Isao H. Inoue	Long-time-constant leaky-integrating oxygen-vacancy drift-diffusion FET for human-interactive spiking reservoir computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zhuocheng Zhang, Zehao Lin, Chang Niu, Mengwei Si, Muhammad Ashraful Alam, Peide D. Ye	Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Navid Anjum Aadit, Masoud Mohseni, Kerem Yunus Camsari	Accelerating Adaptive Parallel Tempering with FPGA-based p-bits.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yuki Okamoto, Yusuke Komura, T. Mizuguchi, Toshihiko Saito, M. Ito, K. Kimura, Tatsuya Onuki, Yoshinori Ando, H. Sawai, T. Murakawa, Hitoshi Kunitake, Takanori Matsuzaki, H. Kimura, M. Fujita, Makoto Ikeda, Shunpei Yamazaki	1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zefu Zhao, Yu-Rui Chen, Yun-Wen Chen, Wan-Hsuan Hsieh, Jer-Fu Wang, Jia-Yang Lee, Yifan Xing, Guan-Hua Chen, Chee Wee Liu	Towards Epitaxial Ferroelectric HZO on n+-Si/Ge Substrates Achieving Record 2Pr = 84 μC/cm² and Endurance > 1E11.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Gyuseong Kang, Hyunjin Shin, Hyuntaek Jung, Sunkyu Lee, Jaeseung Choi 0001, Sangyeop Baek, Hyunsung Jung, Daeshik Kim, Sohee Hwang, Shinhee Han, Yongsung Ji, Sei Seung Yoon	A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Shoubhik Karmakar, Huajun Zhang 0001, Marco Berkhout, Qinwen Fan	A Class-D Piezoelectric Speaker Driver Using A Quadrature Feedback Chopping Scheme achieving 29dB Large-Signal THD+N Improvement.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Seongho Kim, Young-Keun Park, Gyu Soup Lee, Eui Joong Shin, Woon-San Ko, Hi Deok Lee, Ga-Won Lee 0001, Byung Jin Cho	Epitaxial Strain Control of HfxZr1-xO2 with Sub-nm IGZO Seed Layer Achieving EOT=0.44 nm for DRAM Cell Capacitor.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Gajanan Jedhe, Chetan Deshpande, Sushil Kumar, Cheng-Xin Xue, Zijie Guo, Ritesh Garg, Kim Soon Jway, En-Jui Chang, Jenwei Liang, Zhe Wan, Zhenhao Pan	A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yi-Lin Lo, Yu-Chen Lo, Chia-Hsiang Yang	A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	J. Lee, J. Jeong, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens-Yu, D. Greenlaw, Rock-Hyun Baek	Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Chihiro Okada, Sozo Yokogawa, Yuhi Yorikado, Katsumi Honda, Naoki Okuno, Ryohei Ikeno, Makoto Yamakoshi, Hiroshi Ito, Shohei Yoshitsune, Masatsugu Desaki, Shota Hida, Atsushi Nose, Hayato Wakabayashi, Fumihiko Koga	216 fps 672 × 512 pixel 3 μm Indirect Time-of-Flight Image Sensor with 1-Frame Depth Acquisition for Motion Artifact Suppression.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Attilio Belmonte, S. Kundu, S. Subhechha, Adrian Vaisman Chasin, Nouredine Rassoul, Harold Dekkers, H. Puliyalil, F. Seidel, P. Carolan, Romain Delhougne, Gouri Sankar Kar	Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Wooyoung Jo, Sangjin Kim, Juhyoung Lee, Donghyeon Han, Sangyeob Kim, Seungyoon Choi, Hoi-Jun Yoo	NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	S. Ko, J. H. Park, J. H. Bak, H. Jung, J. Shim, D. S. Kim, W. Lim, D.-E. Jeong, J. H. Lee, K. Lee, J.-H. Park, Y. Kim, C. Kim, J. H. Jeong, C. Y. Lee, S. H. Han, Y. Ji, S. H. Hwang, H. J. Shin, Y. J. Song, Y. G. Shin, J. H. Song	Highly Reliable and Manufacturable MRAM embedded in 14nm FinFET node.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jaeyong Jeong, Seong Kwang Kim, Yoon-Je Suh, Jisung Lee, Joonyoung Choi, Juhyuk Park, Joon Pyo Kim, Bong Ho Kim, Younjung Jo, Seung-Young Park, Jongmin Kim, Sanghyeon Kim	Cryogenic RF Transistors and Routing Circuits Based on 3D Stackable InGaAs HEMTs with Nb Superconductors for Large-Scale Quantum Signal Processing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Xiaolin Wang, Zijie Zheng, Qiwen Kong, Leming Jiao, Kaizhen Han, Chen Sun 0010, Zuopu Zhou, Long Liu, Yuye Kang, Gan Liu, Dong Zhang, Xiao Gong	First Demonstration of BEOL-Compatible MFMIS Fe-FETs with 3D Multi-Fin Floating Gate: In-situ ALD-deposited MFM, LCH of 50 nm, > 2×109 Endurance, and 58.3% Area Saving.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kuo-Yu Hsiang, J.-Y. Lee, F.-S. Chang, Z.-F. Lou, Z.-X. Li, Z.-H. Li, J.-H. Chen, C. W. Liu, T.-H. Hou, Min-Hung Lee	FeRAM Recovery up to 200 Periods with Accumulated Endurance 1012 Cycles and an Applicable Array Circuit toward Unlimited eNVM Operations.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim	A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Chih-Hang Tung, Doug C. H. Yu	An Integrated System Scaling Solution for Future High Performance Computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu	An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck	A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Minglei Zhang, Yuefeng Cao, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins	A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka	A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Li Wang, Zilu Liu, C. Patrick Yue	A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and -248.6-dB FoMjitter.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hiroyuki Mizuno	Quantum Computing from Hype to Game Changer.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang 0092, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada	A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Gabriele Atzeni, Can Livanelioglu, Lavinia Recchioni, Sina Arjmandpour, Taekwang Jang	An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier Achieving 0.34 Noise Efficiency Factor and 389 MΩ Input Impedance.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Minyoung Song, Erwin Allebes, Chris Marshall, Anoop Narayan Bhat, Elbert Bechthum, Johan Dijkhuis, Stefano Traferro, Evgenii Tiurin, Peter Vis, Johan H. C. van den Heuvel, Mohieddine El Soussi, Pepijn Boer, Alireza Sheikh, Bernard Meyer, Jiang Liu 0001, Stan van der Ven, Nick Winkel, Martijn Hijdra, Gururaja Kasanadi Ramachandra, Yunus Baykal, Huib Visser, Peng Zhang, Arjan Breeschoten, Yao-Hong Liu, Christian Bachmann	An 8.7 mW/TX, 21 mW/RX 6-to-9GHz IEEE 802.15.4a/4z Compliant IR-UWB Transceiver with Pulse Pre-Emphasis achieving 14mm Ranging Precision.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Whayoung Kim, Jaehyeon Kim, Dongjin Ko, Jun-Hwe Cha, Gyeongcheol Park, Youngbae Ahn, Jong-Young Lee, Minchul Sung, Hyejung Choi, Seung Wook Ryu, Seiyon Kim, Myung-Hee Na, Seonyong Cha	Demonstration of crystalline IGZO transistor with high thermal stability for memory applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Angxiao Yan, Wei Deng 0001, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi	An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Eric Beyne, Anne Jourdain, Gerald Beyer	Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN).	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hui Zhang, Longyang Lin, Qiang Fang, Udara Samurdhi Harshanga Kalingage, Massimo Alioto	Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury	A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	J.-Y. Lee, F.-S. Chang, Kuo-Yu Hsiang, P.-H. Chen, Z.-F. Luo, Z.-X. Li, J.-H. Tsai, C. W. Liu, Min-Hung Lee	3D Stackable Vertical Ferroelectric Tunneling Junction (V-FTJ) with on/off Ratio 1500x, Applicable Cell Current, Self-Rectifying Ratio 1000x, Robust Endurance of 10⁹ Cycles, Multilevel and Demonstrated Macro Operation Toward High-Density BEOL NVMs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang 0019, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu 0004, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu	Building high performance transistors on carbon nanotube channel.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi	A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Xi Chen, Jiaxiang Feng, Aly Shoukry, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu 0001	Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn	A 0.024mm² 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM).	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Fabio Bersano, Michele Aldeghi, Eloi Collette, Michele Ghini, Franco De Palma, Fabian Oppliger, Pasquale Scarlino, Floris Braakman, Martino Poggio, Heike Riel, Gian Salis, Rolf Allenspach, Adrian M. Ionescu	Quantum Dots Array on Ultra-Thin SOI Nanowires with Ferromagnetic Cobalt Barrier Gates for Enhanced Spin Qubit Control.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jie Zhang, Zhuocheng Zhang, Zehao Lin, Ke Xu, Hongyi Dou, Bo Yang, Xinghang Zhang, Haiyan Wang, Peide D. Ye	First Demonstration of BEOL-Compatible Atomic-Layer-Deposited InGaZnO TFTs with 1.5 nm Channel Thickness and 60 nm Channel Length Achieving ON/OFF Ratio Exceeding 1011, SS of 68 mV/dec, Normal-off Operation and High Positive Gate Bias Stability.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Moon Hyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E. J. Chichilnisky, Boris Murmann, Dante G. Muratore	A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Seungheun Song, Taewook Kang, Seungjong Lee, Michael P. Flynn	A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jun-Suk Bang, Dongsu Kim, Young-Hwan Choo, Ik-Hwan Kim, Seungchan Park, Jeongkwang Lee, Sang-Han Lee, Young-Ho Jung, Jae-Young Ko, Sung-Youb Jung, Jae-Yeol Han, Woosik Kim, Ji-Seon Paek, Jongwoo Lee	5G NR RF PA Supply Modulator Supporting 179ns 0.5-to-5.5V Symbol Power Tracking and Envelope Tracking.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Karl Kaiser, Dinesh Patil, Edith Beigné	A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda	A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Chih-Chang Hsieh, Hang-Ting Lue, Yung-Chun Li, Shuo-Nan Hung, Chun-Hsiung Hung, Keh-Chung Wang, Chih-Yuan Lu	Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jungho Lee, Joseph G. Letner, Jongyup Lim, Yi Sun, Seokhyeon Jeong, Yejoong Kim, Beomseo Koo, Gabriele Atzeni, Jiawei Liao, Julianna M. Richie, Elena Della Valle, Paras R. Patel, Taekwang Jang, Cynthia A. Chestek, Jamie Phillips, James D. Weiland, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw	A Wireless Neural Stimulator IC for Cortical Visual Prosthesis.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	T. Patrick Xiao, W. S. Wahby, Christopher H. Bennett, Park Hays, V. Agrawal, Matthew J. Marinella, Sapan Agarwal	Enabling High-Speed, High-Resolution Space-based Focal Plane Arrays with Analog In-Memory Computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung	A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hyo-Jin Park 0002, Joo-Mi Cho, Hyeon-Ji Choi, Chan-Ho Lee, Sung-Wan Hong	96.48% Peak-Efficiency Continuous-Current Step-Up Battery Charger (CC-SUBC) with Dual Energy-Harvesting Sources for Automotive Application.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Chien-Wei Tseng, Zhen Feng, Zichen Fan, Hyochan An, Yunfan Wang, Hun-Seok Kim, David T. Blaauw	A Reconfigurable Analog FIR Filter Achieving -70dB Rejection with Sharp Transition for Narrowband Receivers.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hsin Yu, John Carl Joel Salao Marquez, Chih-Cheng Hsieh	A -20°C~+107°C 52mk-NETD Reference-cell-free 15-bits ROIC for 80×60 Micro-bolometer Thermal Imager.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	C.-L. Lu, C.-H. Chuang, C.-H. Huang, S.-C. Lin, Y.-H. Chang, W.-Y. Lai, M.-H. Chiu, Ming Han Liao, S.-Z. Chang	4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hyeonho Han, Woojun Choi, Jaehyun Kim, Jaesuk Sung, Heonjin Choi, Youngcheol Chae	A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yan-Kui Liang, June-Yang Zheng, Yu-Lon Lin, Wei-Li Li, Yu-Cheng Lu, Dong-Ru Hsieh, Li-Chi Peng, Tsung-Te Chou, Chi-Chung Kei, Chun-Chieh Lu, Huai-Ying Huang, Yuan-Chieh Tseng, Tien-Sheng Chao, Edward Yi Chang, Chun-Hsiung Lin	Aggressively Scaled Atomic Layer Deposited Amorphous InZnOx Thin Film Transistor Exhibiting Prominent Short Channel Characteristics (SS= 69 mV/dec.; DIBL = 27.8 mV/V) and High Gm(802 μS/μm at VDS = 2V).	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Guillaume Schon, Denis Bourke, Pierre-Antoine Doisneau, Thomas Finateu, Adrien Gonzalez, Naoyuki Hanajima, Tahar Hitana, Lucas Janse Van Vuuren, Moataz Kadry, Charles Laurent, Florian Le Goff, Daniel Matolin, Adel Mezaour, Benoît Michel, Thulaxan Naguleswaran, Tjaart Opperman, Patrice Perrin, Etienne Reynaud, Farzaneh Shahrokhi, Hiba Tahachouite, Chen Tianfan, Gerd Van den Branden, Akli Ziram, Jean-Luc Jaffard, Christoph Posch	A 320 x 320 1/5" BSI-CMOS stacked event sensor for low-power vision applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jisan Ahn, Hyun-Su Lee, Kyeongho Eom, Woojoong Jung, Hyung-Min Lee	A 93.5%-Efficiency 13.56-MHz-Bandwidth Optimal On/Off Tracking Active Rectifier with Fully Digital Feedback-Based Delay Control for Adaptive Efficiency Compensation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yoshihide Kihara, Maju Tomura, Wataru Sakamoto, Masanobu Honda, Masayuki Kojima	Beyond 10 μm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Roger Luis Brito Zamparette, Kofi A. A. Makinwa	A 720 nW Current Sensor with 0-to-15 V Input Common-Mode Range and ±0.5% Gain Error from -40 to 85 °C.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yoshinori Nishi, John W. Poulton, Xi Chen 0033, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson 0002, William J. Dally, C. Thomas Gray	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yuye Kang, Kaizhen Han, Yue Chen, Xiao Gong	Thickness-Engineered Extremely-thin Channel High Performance ITO TFTs with Raised S/D Architecture: Record-Low RSD, Highest Moblity (Sub-4 nm TCH Regime), and High VTH Tunability.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Walid M. Hafez, P. Agnihotri, M. Asoro, M. Aykol, B. Bains, R. Bambery, M. Bapna, A. Barik, A. Chatterjee, P. C. Chiu, T. Chu, C. Firby, K. Fischer, M. Fradkin, Hannes Greve, A. Gupta, E. Haralson, M. Haran, Jeffery Hicks, A. Illa, M. Jang, S. Klopcic, M. Kobrinsky, B. Kuns, H.-h. Lai, G. Lanni, S.-H. Lee, N. Lindert, C.-l. Lo, Y. Luo, G. Malyavanatham, B. Marinkovic, Y. Maymon, M. Nabors, J. Neirynck, P. Packan, A. Paliwal, L. Pantisano, Leif Paulson, Padma Penmatsa, Chetan Prasad, Conor Puls, T. Rahman, R. Ramaswamy, S. Samant, Bernhard Sell, K. Sethi, F. Shah, M. Shamanna, K. Shang, Q. Li, M. Sibakoti, J. Stoeger, N. Strutt, R. Thirugnanasambandam, C. Tsai, X. Wang, A. Wang, S.-j. Wu, Q. Xu, X.-h. Zhong, S. Natarajan	Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yusuke Komura, Shoki Miyata, Yuki Okamoto, Yuki Tamatsukuri, Hiroki Inoue, Toshihiko Saito, Munehiro Kozuma, Hidetomo Kobayashi, Tatsuya Onuki, Yuichi Yanagisawa, Toshihiko Takeuchi, Yutaka Okazaki, Hitoshi Kunitake, Daiki Nakamura, Takaaki Nagata, Yasumasa Yamane, Makoto Ikeda, Shih-Ci Yen, Chuan-Hua Chang, Wen-Hsiang Hsieh, Hiroshi Yoshida, Min-Cheng Chen, Ming-Han Liao, Shou-Zen Chang, Shunpei Yamazaki	Two-Dimensionally Arranged Display Drivers Achieved by OS/Si Structure.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	N. Ishihara, Y. Shimada, T. Ochi, S. Seto, H. Matsuo, H. Yamashita, S. Morita, M. Ukishima, K. Uejima, Y. Arayashiki, S. Kajiwara, A. Murayama, K. Nishiyama, K. Sugimae, S. Mori, Y. Saito, T. Shundo, A. Maeda, H. Kamiya, Y. Uchiyama, M. Fujiwara, F. Aiso, K. Sekine, N. Ohtani	Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical Si Channel in Ultra-High (> 300 Layers) 3D Flash Memory.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Victor Vega-Gonzalez, D. Radisic, Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster, Y. Oniki, P. Puttarame, Kevin Vandersmissen, J. P. Soulie, A. Peter, A. Sepulveda, D. Batuk, G. T. Martinez, Olivier Richard, Jürgen Bömmels, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi, S. Park, Zsolt Tokei	Integration of a Stacked Contact MOL for Monolithic CFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Takafumi Takatsuka, Jun Ogi, Yasuji Ikeda, Kazuki Hizu, Yutaka Inaoka, Shunsuke Sakama, Iori Watanabe, T. Ishikawa, Shohei Shimada, Junki Suzuki, Hidenori Maeda, Kenji Toshima, Yusuke Nonaka, Akifumi Yamamura, Hideki Ozawa, Fumihiko Koga, Yusuke Oike	A 3.36 µm-pitch SPAD photon-counting image sensor using clustered multi-cycle clocked recharging technique with intermediate most-significant-bit readout.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Dexuan Huo, Jilin Zhang, Xinyu Dai, Jian Zhang, Chunqi Qian, Kea-Tiong Tang, Hong Chen 0002	ANP-G: A 28nm 1.04pJ/SOP Sub-mm2 Spiking and Back-propagation Hybrid Neural Network Asynchronous Olfactory Processor Enabling Few-shot Class-incremental On-chip Learning.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yoontae Jung, Sein Oh, Jimin Koo, Seunga Park, Ji-Hoon Suh, Donghee Cho, Sohmyung Ha, Minkyu Je	A 187dB FoMS 46fJ/Conv 2nd-order Highpass Δ∑ Capacitance-to-Digital Converter.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Wei Wang, Liwen Jiang, Shayok Dutta, Yumin Su, Zhiyu Chen 0003, Zhanghao Yu, Caleb Kemere, Kaiyuan Yang 0001	A 36nW CMOS Temperature Sensor with <0.1K Inaccuracy and Uniform Resolution.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	En-Jui Chang, Cheng-Xin Xue, Chetan Deshpande, Gajanan Jedhe, Jenwei Liang, Chih-Chung Cheng, Hung-Wei Lin, Chia-Da Lee, Sushil Kumar, Kim Soon Jway, Zijie Guo, Ritesh Garg, Allen-Cl Lu, Chien-Hung Lin, Meng-Han Hsieh, Tsung-Yao Lin, Chih-Cheng Chen	A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zuocheng Cai, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi	HZO Scaling and Fatigue Recovery in FeFET with Low Voltage Operation: Evidence of Transition from Interface Degradation to Ferroelectric Fatigue.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Song Chen, Chiao Liu, Lyle Bainbridge, Qing Chao, Ramakrishna Chilukuri, Wei Gao, Andrew P. Hammond, Tsung-Hsun Tsai, Ken Miyauchi, Isao Takayanagi, Masato Nagamatsu, Hirofumi Abe, Kazuya Mori, Masayuki Uno, Toshiyuki Isozaki, Rimon Ikeno, Hsin-Li Chen, Chih-Hao Lin, Wen-Chien Fu, Shou-Gwo Wuu	A 3.96μm, 124dB Dynamic Range, 6.2mW Stacked Digital Pixel Sensor with Monochrome and Near-Infrared Dual-Channel Global Shutter Capture.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Po-Hsuan Chang, Anirban Samanta, Peng Yan, Mingye Fu, Yu Zhang, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, Dedeepya Annabattuni, David Scott, Robert Patti, Yang-Hang Fan, Yuanming Zhu, S. J. Ben Yoo, Samuel Palermo	A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu 0009, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang	A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu 0004, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu	Scaled contact length with low contact resistance in monolayer 2D channel transistors.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jaehun Jeong, Sanghyeon Lee, Sada-Aki Masuoka, Shincheol Min, Sanghoon Lee, Seungkwon Kim, Taehun Myung, Byungha Choi, Chang-Woo Sohn, Sung Won Kim, Jeongmin Choi, Jungmin Park, Hyungjong Lee, Taeyoung Kim, Seokhoon Kim, Yuri Yasuda-Masuoka, Ja-Hum Ku, Gitae Jeong	World's First GAA 3nm Foundry platform Technology (SF3) with Novel Multi-Bridge-Channel-FET (MBCFET™) Process.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Han-Gyeol Mun, Hyunwoo Son, Seunghyun Moon, Jaehyun Park, ByungJun Kim, Jae-Yoon Sim	A 28 nm 66.8 TOPS/W Sparsity-Aware Dynamic-Precision Deep-Learning Processor.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Eunsung Park, Won-Yong Ha, Doyoon Eom, Dae-Hwan Ahn, Hyuk An, Suhyun Yi, Kyung-Do Kim, Jongchae Kim, Woo-Young Choi, Myung-Jae Lee	Doping-Optimized Back-illuminated Single-Photon Avalanche Diode in Stacked 40 nm CIS Technology Achieving 60% PDP at 905 nm.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung	A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Gaurav Thareja, Ashish Pal, Xingye Wang, Sefa Dag, Shi You, Shashank Sharma, Qing Zhu, Carmen L. Cervantes, Shinjae Hwang, Matthew Spuller, Ben Ng, Pradeep S. Kumar, Norman Tam, Max Gage, Sameer Deshpande, Zhiyuan Wu, Alexander Jansen, Liton Dey, Feng Chen, Xianjin Xie, Keyvan Kashefizadeh, Vinod Reddy, Andy Lo, Zhebo Chen, Sidney Huey, Jianshe Tang, He Ren, Mehul Naik, Brian Brown, Sree Kesapragada, Buvna Ayyagari-Sangamalli, El Mehdi Bazizi, Xianmin Tang	BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Gerui Zheng, Yuxuan Wang, Haiwen Xu, Rami Khazaka, Lutz Muehlenbein, Sheng Luo, Xuanqi Chen, Rui Shao, Zijie Zheng, Gengchiau Liang, Xiao Gong	Record High Active Boron Doping using Low Temperature In-situ CVD: Enabling Sub-5×10-10 Ω-cm2 ρc from Cryogenic (5 K) to Room Temperature.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	N. Breil, B.-C. Lee, J. Avila Avendano, J. Jewell, M. Vellaikal, E. Newman, E. M. Bazizi, A. Pal, L. Liu, Oleg Gluschenkov, A. Greene, S. Mochizuki, Nicolas Loubet, B. Colombeau, B. Haran	Contact Cavity Shaping and Selective SiGe: B Low-Temperature Epitaxy Process Solution for sub 10-9 Ω.cm2 Contact Resistivity in Nonplanar FETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Alessandro Novello, Gabriele Atzeni, Tim Keller, Taekwang Jang	A 4.1W/mm² Peak Power Density and 77% Peak Efficiency Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators and a Resonant LC Flying Impedance in 22nm FDSOI CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Seokchan Song, Donghyeon Han, Sangjin Kim, Sangyeob Kim, Gwangtae Park, Hoi-Jun Yoo	GPPU: A 330.4-μJ/ task Neural Path Planning Processor with Hybrid GNN Acceleration for Autonomous 3D Navigation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Norio Chujo, Koji Sakui, Shinji Sugatani, Hiroyuki Ryoson, Tomoji Nakamura, Takayuki Ohba	Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Raja Swaminathan, Michael J. Schulte, Brett Wilkerson, Gabriel H. Loh, Alan Smith, Norman James	AMD InstinctTM MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sonu Hooda, Chun-Kuei Chen, Manohar Lal, Shih-Hao Tsai, Evgeny Zamburg, Aaron Voon-Yew Thean	Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Leming Jiao, Kaizhen Han, Zuopu Zhou, Zijie Zheng, Xiaolin Wang, Qiwen Kong, Yuye Kang, Jishen Zhang, Long Liu, Xiao Gong	First Demonstration of BEOL-Compatible Write-Enhanced Ferroelectric-Modulated Diode (FMD): New Possibility for Oxide Semiconductor Memory Devices.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yijie Wei, Xi Chen, Jie Gu 0001	Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers	A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sharadindu Gopal Kirtania, Khandker Akif Aabrar, Asif Islam Khan, Shimeng Yu, Samyak Datta	Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF