Search results for "C-Testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
127	Yogesh Singh, Anju Saha	A Metric-Based Approach to Assess Class Testability.	XP	2008	DBLP DOI BibTeX RDF
112	Jeffrey M. Voas, Keith W. Miller 0001	Software Testability: The New Verification.	IEEE Softw.	1995	DBLP DOI BibTeX RDF
110	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
107	Jerry Gao 0002, Ming-Chih Shih	A Component Testability Model for Verification and Measurement.	COMPSAC (2)	2005	DBLP DOI BibTeX RDF	component testability, component testing and component-based software testing, testability analysis, testability measurement
107	Harry Hengster, Rolf Drechsler, Bernd Becker 0001	On local transformations and path delay fault testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	path delay fault model, testability preserving transformations, testability inproving transformations, design for testability
99	Dong Xiang, Yi Xu, Hideo Fujiwara	Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	inversion parity, nonscan design for testability, sequential depth for testability, Conflict, testability measure, partial scan design
92	Amey Karkare, Manoj Singla, Ajai Jain	Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit.	VLSI Design	1998	DBLP DOI BibTeX RDF	Testability Preserving Transformations, Testability Enhancing Transformations, DFT, Testability, Delay Faults
82	Benoit Baudry, Yves Le Traon, Gerson Sunyé, Jean-Marc Jézéquel	Measuring and Improving Design Patterns Testability.	IEEE METRICS	2003	DBLP DOI BibTeX RDF
81	Alvin Jee, F. Joel Ferguson	A methodolgy for characterizing cell testability.	VTS	1997	DBLP DOI BibTeX RDF	cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects
80	Xinli Gu	RT level testability-driven partitioning.	VTS	1995	DBLP DOI BibTeX RDF	testability-driven partitioning, RT level designs, hard-to-test points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, built-in self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques
78	Raees Ahmad Khan, Khurram Mustafa	Metric based testability model for object oriented design (MTMOOD).	ACM SIGSOFT Softw. Eng. Notes	2009	DBLP DOI BibTeX RDF	software characteristics, software testability, model, design, object oriented, metrics
78	Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang	Novel techniques for improving testability analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns
78	Antonia Bertolino, Lorenzo Strigini	On the Use of Testability Measures for Dependability Assessment.	IEEE Trans. Software Eng.	1996	DBLP DOI BibTeX RDF	ultra-high reliability, software testing, error, Bayesian inference, testability, failure, fault, test oracle, reliability assessment
76	Frank F. Hsu, Janak H. Patel	A distance reduction approach to design for testability.	VTS	1995	DBLP DOI BibTeX RDF	distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
76	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
76	Taghi M. Khoshgoftaar, Robert M. Szabo, Jeffrey M. Voas	Detecting program modules with low testability.	ICSM	1995	DBLP DOI BibTeX RDF	aircraft computers, program module detection, low testability, static software product measures, dynamic quality measure, real time avionics software system, component program modules, classification performance, discriminant modeling methodology, real-time systems, software quality, software metrics, program testing, testability, testability analysis, principal components
75	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Easily Testable Cellular Carry Lookahead Adders.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
74	Indradeep Ghosh, Niraj K. Jha, Sujit Dey	A low overhead design for testability and test generation technique for core-based systems-on-a-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
73	Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara	BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test
73	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz	LOT: logic optimization with testability-new transformations using recursive learning.	ICCAD	1995	DBLP DOI BibTeX RDF	EX-OR gates, logic optimization with testability, multi-level logic circuits, tstfx, logic design, combinational circuits, logic CAD, gate level, random-pattern testability, recursive learning
72	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
70	Nguyen Thanh Binh 0002, Michel Delaunay, Chantal Robach	Testability Analysis Applied to Embedded Data-flow Software.	QSIC	2003	DBLP DOI BibTeX RDF	Data-flow Software, Software Measurement, Testability Analysis
70	Sandhya Seshadri, Michael S. Hsiao	Behavioral-Level DFT via Formal Operator Testability Measures.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	behavioral level, operator testability, value range, SSA representation, DFT
70	Martin R. Woodward, Zuhoor A. Al-Khanjari	Testability, fault size and the domain-to-range ratio: An eternal triangle.	ISSTA	2000	DBLP DOI BibTeX RDF	domain-to-range ratio, fault size, controllability, observability, testability
70	Charles E. Stroud, Ahmed E. Barbour	Testability and test generation for majority voting fault-tolerant circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults
69	Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara	A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	strong testability, partially strong testability, complete fault efficiency, design-for-testability, data paths
69	Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara	Strong self-testability for data paths high-level synthesis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment
69	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
69	Yves Le Traon, Chantal Robach	Testability analysis of co-designed systems.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	co-designed data-flow specifications, high level testability analysis, information transfer graph, bipartite directed graph, SATAN tool, computer assisted specification diagram, all-nodes criterion, all-paths criterion, multiple clue strategy, start big strategy, diagnosis quality factor, software components testability, formal specification, fault diagnosis, program testing, data flow analysis, computer aided software engineering, hardware description languages, data flow graphs, testability analysis, automatic test software, functional specification, test set generation, avionics systems, hardware modelling
67	Josef Strnadel	TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path.	DSD	2008	DBLP DOI BibTeX RDF
67	Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin	Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations.	VLSI Design	1999	DBLP DOI BibTeX RDF
67	Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza	ALADIN: a multilevel testability analyzer for VLSI system design.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
66	Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel	Enhancing high-level control-flow for improved testability.	ICCAD	1996	DBLP DOI BibTeX RDF	synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description
66	Kee Sup Kim, Charles R. Kime	Partial scan flip-flop selection by use of empirical testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	scan flip-flop selection, serial scan, design for testability, testability, partial scan
64	Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui	PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM
62	Laurence Tianruo Yang, Zebo Peng	Incremental Testability Analysis for Partial Scan Selection and Design Transformations.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	incremental testability analysis, partial scan selection, design transformation, register transfer level, high-level test synthesis
62	Pu-Lin Yeh, Jin-Cherng Lin	Software Testability Measurements Derived from Data Flow Analysis.	CSMR	1998	DBLP DOI BibTeX RDF	software testability, software testing, software measurement, data flow, testing criteria
62	Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	Respecification, Synthesis for Testability, Don't Cares, High Level Testing
62	Jeffrey M. Voas	Software testability measurement for intelligent assertion placement.	Softw. Qual. J.	1997	DBLP DOI BibTeX RDF	testing, observability, testability, failure, fault, assertions, fault propagation
62	Prashant S. Parikh, Miron Abramovici	Testability-based partial scan analysis.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testability cost, sensitivity analysis, partial scan
61	Hiroaki Ueda, Kozo Kinoshita	Low power design and its testability.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
61	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
59	Tsung-Han Tsai, Chin-Yu Huang, Jun-Ru Chang	A Study of Applying Extended PIE Technique to Software Testability Analysis.	COMPSAC (1)	2009	DBLP DOI BibTeX RDF
59	Dong Xiang, Shan Gu, Hideo Fujiwara	Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
59	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
59	Sandeep Bhatia, Niraj K. Jha	Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
58	Tomokazu Yoneda, Hideo Fujiwara	Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability
58	Tomokazu Yoneda, Hideo Fujiwara	A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	consecutive transparency, core-based systems-on-a-chip, design for testability, test access mechanism, consecutive testability
58	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
58	Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker 0001	Testability of 2-Level AND/EXOR Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	AND/EXOR, 2-level circuits, synthesis for testability, random pattern testability
58	Giacomo Buonanno, Franco Fummi, Donatella Sciuto	TIES: A testability increase expert system for VLSI design.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	design for testability techniques, DfT advisor, testability analysis, testable design
58	João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves	A methodology for testability enhancement at layout level.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	physical design rules for testability, simulation, fault modeling, testability analysis
55	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Improving testability and soft-error resilience through retiming.	DAC	2009	DBLP DOI BibTeX RDF	testability, soft errors, retiming
55	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing
55	Ronny Kolb, Dirk Muthig	Making testing product lines more efficient by improving the testability of product line architectures.	ROSATEA	2006	DBLP DOI BibTeX RDF	evaluation, design, architecture, testing, software product line, testability
55	Jaan Raik, Tanel Nõmmeots, Raimund Ubar	A New Testability Calculation Method to Guide RTL Test Generation.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	test pattern generation, register-transfer level, decision diagrams, testability measures
55	Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee	A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality.	ISQED	2000	DBLP DOI BibTeX RDF	Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing
55	Kelly A. Ockunzzi, Christos A. Papachristou	Testability Enhancement for Control-Flow Intensive Behaviors.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral testability analysis and insertion, BIST, test synthesis
55	Zdenek Kotásek, F. Zboril	RT level testability analysis to reduce test application time.	EUROMICRO	1997	DBLP DOI BibTeX RDF	register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction
55	Harry Hengster, Rolf Drechsler, Bernd Becker 0001	On the application of local circuit transformations with special emphasis on path delay fault testability.	VTS	1995	DBLP DOI BibTeX RDF	local circuit transformations, path delay fault testability, SALT, logic testing, delays, integrated circuit testing, automatic testing
55	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating testability considerations in high-level synthesis.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
54	Franco Fummi, Donatella Sciuto, M. Serro	Synthesis for testability of large complexity controllers.	ICCD	1995	DBLP DOI BibTeX RDF	large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
53	Sandhya Seshadri, Michael S. Hsiao	Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	behavioral level, value range, SSA representation, design for testability
51	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
51	Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina	Testability Estimation Based on Controllability and Observability Parameters.	DSD	2006	DBLP DOI BibTeX RDF
51	Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang	Design-for-testability and fault-tolerant techniques for FFT processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
51	Dong Xiang, Shan Gu, Hideo Fujiwara	Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
51	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO: regular expression-based register-transfer level testability analysis and optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
51	A. N. Trahtman	Piecewise and Local Threshold Testability of DFA.	FCT	2001	DBLP DOI BibTeX RDF	locally threshold testable, piecewise testable, locally testable, syntactic semigroup, algorithm, automaton, transition graph
51	Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang	TAIR: testability analysis by implication reasoning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
51	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz	LOT: Logic Optimization with Testability. New transformations for logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
51	Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	controller resynthesis, test synthesis, high-level testing
51	Hingsam S. Fung, Sanford Hirschhorn, R. Kulkarni	Design for testability in a silicon compilation environment.	DAC	1985	DBLP DOI BibTeX RDF
50	Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara	Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability.	ITC	2003	DBLP DOI BibTeX RDF	design for testability, system-on-a-chip, test scheduling, test access mechanism, consecutive testability
50	Frank F. Hsu, Janak H. Patel	Design for Testability Using State Distances.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	state distance, finite-state-machine, design-for-testability, synthesis-for-testability
50	Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel	Testability Insertion in Behavioral Descriptions.	ISSS	1996	DBLP DOI BibTeX RDF	synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description
50	Yu Fang, Alexander Albicki	Efficient testability enhancement for combinational circuit.	ICCD	1995	DBLP DOI BibTeX RDF	testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
50	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
50	Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar	Testability-oriented channel routing.	VLSI Design	1995	DBLP DOI BibTeX RDF	IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield
50	Fabrizio Lombardi, Donatella Sciuto	Constant testability of combinational cellular tree structures.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Constant testability, testing, design for testability, finite automata, tree structures
47	Phil McMinn	Search-based failure discovery using testability transformations to generate pseudo-oracles.	GECCO	2009	DBLP DOI BibTeX RDF	non-testable program, pseudo-oracle, search-based software testing, testability transformation, program transformation, oracle
47	Misko Hevery	Testability explorer: using byte-code analysis to engineer lasting social changes in an organization's software development process.	OOPSLA Companion	2008	DBLP DOI BibTeX RDF	byte-code analysis, refactoring, unit testing, testability, social engineering
47	Michel Jaring, René L. Krikhaar, Jan Bosch	Modeling Variability and Testability Interaction in Software Product Line Engineering.	ICCBSS	2008	DBLP DOI BibTeX RDF	software product line, variability, testability
47	Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen	A Statistic-Based Approach to Testability Analysis.	ISQED	2008	DBLP DOI BibTeX RDF	fault detection probability, controllability, observability, Testability analysis
47	Lian Yu, Lifeng Xu, Guanzhu Wang, Chang Yan Chi, Wenping Xiao, Hui Su	Testability and Test Framework for Collaborative Real-Time Editing Tools.	QSIC	2007	DBLP DOI BibTeX RDF	timeline diagram, grey-box testing, visualization, collaboration, testability, test framework
47	Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto	Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Testing of embedded systems, VHDL, ATPG, fault modeling, testability analysis
47	Zuhoor A. Al-Khanjari, Martin R. Woodward, Haider Ali Ramadhan	Critical Analysis of the PIE Testability Technique.	Softw. Qual. J.	2002	DBLP DOI BibTeX RDF	PIE technique, mutant schemata, testability, sensitivity, infection
47	Nguyen Thanh Binh 0002, Michel Delaunay, Chantal Robach	Testability Analysis for Software Components.	ICSM	2002	DBLP DOI BibTeX RDF	Data-flow Systems, Software Metrics, Testability Analysis, Testing Criteria
47	Harry Hengster, Bernd Becker 0001	Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.	FTCS	1999	DBLP DOI BibTeX RDF	EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits
47	Kamel Karoui, Abderrazak Ghedamsi, Rachida Dssouli	A Study of Some Influencing Factors in Testability and Diagnostics Based on FSMs.	ISCC	1999	DBLP DOI BibTeX RDF	Design, Controllability, Abstraction, Fuzziness, Testability, Diagnostics, Distinguishability
47	Kowen Lai, Christos A. Papachristou, Mikhail Baklashov	BIST testability enhancement using high level test synthesis for behavioral and structural designs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	BIST testability, behavioral designs, industrial benchmark, controllability, built-in self test, observability, DFT, transparency, fidelity, structural designs, high level test synthesis
47	Marc Perbost, Ludovic Le Lan, Christian Landrault	Automatic Testability Analysis of Boards and MCMs at Chip Level.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	DFT, testability analysis, MCM
47	Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz	On minimizing the number of test points needed to achieve complete robust path delay fault testability.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion
47	Johannes Steensma, Werner Geurts, Francky Catthoor, Hugo De Man	Testability analysis in high level data path synthesis.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Data path testing, high level synthesis, test pattern generation, testability analysis
46	Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki	A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
46	Srivaths Ravi 0001, Niraj K. Jha	Test synthesis of systems-on-a-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
46	Frank F. Hsu, Janak H. Patel	High-Level Controllability and Observability Analysis for Test Synthesis.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	controllability, observability, high-level test synthesis, behavioral modification
46	Christos A. Papachristou, Mikhail Baklashov, Kowen Lai	High-Level Test Synthesis for Behavioral and Structural Designs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	built-in self test, DFT, test synthesis
44	Dong Xiang, Janak H. Patel	Partial Scan Design Based on Circuit State Information and Functional Analysis.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Valid state, invalid state, testability improvement potential, conflict, testability measure, partial scan design
44	Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki	Cost/Quality Trade-off in Synthesis for BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	DFT reuse, BIST, synthesis for testability, testability analysis