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Publication types (Num. hits)
article(4437) book(1) data(5) incollection(32) inproceedings(7361) phdthesis(56) proceedings(1)
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Found 11893 publication records. Showing 11893 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
97Wei-lun Kao, Ravishankar K. Iyer, Dong Tang FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior under Faults. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF FINE, fault injection and monitoring environment, UNIX system behavior, hardware-induced software errors, fault injector, analysis utilities, SunOS 4.1.2, transient Markov reward analysis, bus faults, CPU faults, pointer faults, software tools, Unix, program testing, system monitoring, software faults, software monitor, workload generator
92Bin Liu, Fabrizio Lombardi, Wei-Kang Huang Testing programmable interconnect systems: an algorithmic approach. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
84Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell Functional test generation for path delay faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
74Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck Deterministic test generation for non-classical faults on the gate level. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
72Irith Pomeranz, Sudhakar M. Reddy Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
67Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu On the characterization and efficient computation of hard-to-detect bridging faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
63Bruce F. Cockburn, Janusz A. Brzozowski Near-optimal tests for classes of write-triggered coupling faults in RAMs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF toggling faults, lower bounds, coupling faults, RAM testing, optimal tests
62Irith Pomeranz, Sudhakar M. Reddy On achieving complete fault coverage for sequential machines. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
59Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar Primitive delay faults: identification, testing, and design for testability. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
58Michiel M. Ligthart, Rudi J. Stans A fault model for PLAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
58Irith Pomeranz, Sudhakar M. Reddy Partitioned n-detection test generation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets
57João Durães, Henrique Madeira Emulation of Software Faults: A Field Data Study and a Practical Approach. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF software reliability, Fault injection, software faults
57Amitabha Bagchi, Ankur Bhargava, Amitabh Chaudhary, David Eppstein, Christian Scheideler The effect of faults on network expansion. Search on Bibsonomy SPAA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF d-dimensional mesh, faulty networks, expansion, random faults
57Mark C. Hansen, John P. Hayes High-level test generation using physically-induced faults. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test
57Yashwant K. Malaiya, Stephen Y. H. Su Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1981 DBLP  DOI  BibTeX  RDF modeling of faults, Markov model, transient faults, multiple faults, fault-tolerant system, reliability analysis, intermittent faults, permanent faults, Fault-tolerant design, reliability evaluation, reconfiguration scheme, hardware redundancy
55Kwang-Ting Cheng, Hsi-Chuan Chen Classification and identification of nonrobust untestable path delay faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
55Petru Cascaval, Stuart Bennett, Corneliu Hutanu Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF fault simulation, memory testing, march test, coupling faults, functional faults
55Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik March LR: a test for realistic linked faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults
54Tomislav Lovric Systematic and Design Diversity - Software Techniques for Hardware Fault Detection. Search on Bibsonomy EDCC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF design faults, operational faults, fault detection coverage, relative test, absolute test, software implemented hardware-fault injection, systematic diversity, Virtual Duplex System, self-checking, design diversity, fail-safe
53Thomas J. Ostrand, Elaine J. Weyuker, Robert M. Bell Predicting the Location and Number of Faults in Large Software Systems. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF software testing, prediction, empirical study, Software faults, regression model, fault-prone
53Olivier Contant, Stéphane Lafortune, Demosthenis Teneketzis Diagnosis of Intermittent Faults. Search on Bibsonomy Discret. Event Dyn. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF fault diagnosis, fault detection, diagnosability, intermittent faults
53Henrique Madeira, Diamantino Costa, Marco Vieira On the Emulation of Software Faults by Software Fault Injection. Search on Bibsonomy DSN The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Fault injection, software faults, fault classification
53Subhachandra Chandra, Peter M. Chen Whither Generic Recovery from Application Faults? A Fault Study using Open-Source Software. Search on Bibsonomy DSN The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Heisenbugs, Software, Recovery, Faults, Transient
53Cecilia Metra, Michele Favalli, Bruno Riccò Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults
52Udo Mahlstedt, Jürgen Alt, Matthias Heinitz CURRENT: a test generation system for IDDQ testing. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
52V. Kim, T. Chen Assessing SRAM test coverage for sub-micron CMOS technologies. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits
51Charles J. Colbourn, Daniel W. McClary Locating and detecting arrays for interaction faults. Search on Bibsonomy J. Comb. Optim. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Disjunct matrix, Locating array, Defecting array, Covering array, Orthogonal array, Cover-free family, Factorial design
51Hyunsook Do, Gregg Rothermel On the Use of Mutation Faults in Empirical Assessments of Test Case Prioritization Techniques. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF program mutation, empirical studies, Regression testing, test case prioritization
51Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen Identification of robust untestable path delay faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
51Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara Compact test generation for bridging faults under IDDQ testing. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
51Bruce F. Cockburn Deterministic tests for detecting singleV-coupling faults in RAMs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF V-coupling faults, lower bounds, Functional tests, pattern-sensitive faults, RAM testing
51El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny On the generation of test patterns for multiple faults. Search on Bibsonomy J. Electron. Test. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis
50David Walker 0001, Lester W. Mackey, Jay Ligatti, George A. Reis, David I. August Static typing for a faulty lambda calculus. Search on Bibsonomy ICFP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF transient hardware faults, fault tolerance, type systems, lambda calculus, reliable computing, typed intermediate languages, soft faults
49Irith Pomeranz, Sudhakar M. Reddy On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance
49Norman E. Fenton, Niclas Ohlsson Quantitative Analysis of Faults and Failures in a Complex Software System. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Software faults and failures, empirical studies, software metrics
49Srikanth Venkataraman, W. Kent Fuchs A deductive technique for diagnosis of bridging faults. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Diagnosis, Bridging faults, Deduction
49Jack R. Smith, Tian Xia, Charles E. Stroud An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF stuck-at faults, bridging faults, delay faults
49Yuyun Liao, D. M. H. Walker Optimal voltage testing for physically-based faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
48Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki Experimental fault analysis of 1 Mb SRAM chips. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips
48Kuo-Chung Tai Theory of Fault-Based Predicate Testing for Computer Programs. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF predicate testing, boolean operator faults, relational operator faults, off-by-$epsilon$ faults, Software testing, fault-based testing
48K. Vijayananda Distributed fault detection in communication protocols using extended finite state machines. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines
48Andrej Zemva, Franc Brglez Detectable perturbations: a paradigm for technology-specific multi-fault test generation. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
48Jan Schat Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
48Joaquin Gracia, Luis J. Saiz, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil Analysis of the influence of intermittent faults in a microcontroller. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
48Hyunsook Do, Gregg Rothermel A Controlled Experiment Assessing Test Case Prioritization Techniques via Mutation Faults. Search on Bibsonomy ICSM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
48Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu On the Characterization of Hard-to-Detect Bridging Faults. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee Analog circuit equivalent faults in the D.C. domain. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits
47Irith Pomeranz, Sudhakar M. Reddy Classification of Faults in Synchronous Sequential Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF undetectable faults, initial conditions, partially detectable faults, synchronization mode, free mode, logic testing, sequential circuits, synchronisation, fault location, synchronous sequential circuits, combinatorial circuits, test sequence, faults classification, redundant faults
46Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren Quantitative Analysis of In-Field Defects in Image Sensor Arrays. Search on Bibsonomy DFT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Sandeep S. Kulkarni, Ali Ebnenasir Automated Synthesis of Multitolerance. Search on Bibsonomy DSN The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Fault-tolerance, Formal methods, Distributed programs, Program synthesis, Automatic addition of fault-tolerance
46Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker A circuit level fault model for resistive bridges. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF fault models, bridge faults, delay faults
46Samy Makar, Edward J. McCluskey Checking experiments to test latches. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
46Said Hamdioui, Ad J. van de Goor Efficient Tests for Realistic Faults in Dual-Port SRAMs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Multiport/single-port memories, weak faults, fault models, fault coverage, march tests
46Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF digital circuit testing, test generation, fault models, delay test, path delay faults
46Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour Diagnosing multiple transition faults in the absence of timing information. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF diagnosis, multiple faults, delay faults, incremental, transition faults
45Irith Pomeranz, Sudhakar M. Reddy Test enrichment for path delay faults using multiple sets of target faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
44Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara Single-control testability of RTL data paths for BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
44Bo Yao, Irith Pomeranz, Sudhakar M. Reddy Deterministic broadside test generation for transition path delay faults. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF broadside test, deterministic test generation, path delay fault, transition fault
44Sultan M. Al-Harbi, Fadel Noor, Fadi M. Al-Turjman March DSS: A New Diagnostic March Test for All Memory Simple Static Faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
44Abhishek B. Sharma, Leana Golubchik, Ramesh Govindan On the Prevalence of Sensor Faults in Real-World Deployments. Search on Bibsonomy SECON The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
44Man Fai Lau, Ying Liu, Yuen-Tak Yu Detecting Double Faults on Term and Literal in Boolean Expressions. Search on Bibsonomy QSIC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
44Evangelos Kranakis, Michel Paquette, Andrzej Pelc Communication in Networks with Random Dependent Faults. Search on Bibsonomy MFCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF dependent faults, crash faults, Fault-tolerance, communication, network connectivity
44József Sziray Test Calculation for Logic and Delay Faults in Digital Circuits. Search on Bibsonomy MTV The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic
44Ramesh C. Tekumalla, Premachandran R. Menon On Redundant Path Delay Faults in Synchronous Sequential Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF functional sensitizability, sequential circuits, testability, Path delay faults, redundant faults
44Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults
44Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli Compact and complete test set generation for multiple stuck-faults. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Multiple stuck faults, complete test set generation, irrepressible faults
42James H. Andrews, Lionel C. Briand, Yvan Labiche Is mutation an appropriate tool for testing experiments? Search on Bibsonomy ICSE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF hand-seeded faults, mutants, real faults
42Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor Memory Fault Modeling Trends: A Case Study. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF static faults, fault models, fault coverage, memory tests, dynamic faults, data backgrounds
42Zaid Al-Ars, Ad J. van de Goor Modeling Techniques and Tests for Partial Faults in Memory Devices. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF partial faults, completing operations, fault models, memory testing, DRAMs, defect simulation
42Ulrich Schmid 0001, Bettina Weiss, John M. Rushby Formally Verified Byzantine Agreement in Presence of Link Faults. Search on Bibsonomy ICDCS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF assumption coverage, formal verification, lower bounds, fault models, consensus, Byzantine agreement, Fault-tolerant distributed systems, link faults, impossibility results
40Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji Modified Stability Checking for On-line Error Detection. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF crosstalk faults and transient faults, SEU testing, modified stability checking, delay faults, self-checking circuits, Concurrent testing, on-line error detection
40Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy Fsimac: a fault simulator for asynchronous sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
40Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve Accurate microarchitecture-level fault modeling for studying hardware faults. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
40Man Fai Lau, Ying Liu, Yuen-Tak Yu On Detection Conditions of Double Faults Related to Terms in Boolean Expressions. Search on Bibsonomy COMPSAC (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Irith Pomeranz, Sudhakar M. Reddy On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Joakim Aidemark, Peter Folkesson, Johan Karlsson On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy. Search on Bibsonomy IOLTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Sultan M. Al-Harbi, Sandeep K. Gupta 0001 Generating Complete and Optimal March Tests for Linked Faults in Memories. Search on Bibsonomy VTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40João Durães, Henrique Madeira Emulation of Software Faults by Educated Mutations at Machine-Code Level. Search on Bibsonomy ISSRE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Xiaoding Chen, Michael S. Hsiao Characteristic faults and spectral information for logic BIST. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. Search on Bibsonomy PRDC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Piotr R. Sidorowicz Modeling and Testing Transistor Faults in Content-Addressable Memories. Search on Bibsonomy MTDT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
40Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
40Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal Fast identification of untestable delay faults using implications. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
40Irith Pomeranz, Sudhakar M. Reddy On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
40A. Jefferson Offutt, Jane Huffman Hayes A Semantic Model of Program Faults. Search on Bibsonomy ISSTA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
40Nicola Santoro, Peter Widmayer Distributed Function Evaluation in the Presence of Transmission Faults. Search on Bibsonomy SIGAL International Symposium on Algorithms The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
40Niraj K. Jha, Qiao Tong Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
40Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Faults in scan cells, stuck-at and stuck-on faults
40Joonhwan Yi, John P. Hayes The Coupling Model for Function and Delay Faults. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF test generation, fault modeling, delay faults, functional faults
40Toshiyuki Maeda, Kozo Kinoshita Memory reduction of IDDQ test compaction for internal and external bridging faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
40Kuen-Jong Lee, Jing-Jou Tang Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
40Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
40Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham A novel test generation approach for parametric faults in linear analog circuits . Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
40Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez Diagnostic of path and gate delay faults in non-scan sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
39Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre Fault Collapsing via Functional Dominance. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Michiko Inoue, Emil Gizdarski, Hideo Fujiwara A class of sequential circuits with combinational test generation complexity under single-fault assumption. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
38René David, Antoine Fuentes, Bernard Courtois Random Pattern Testing Versus Deterministic Testing of RAM's. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1989 DBLP  DOI  BibTeX  RDF random pattern testing, double faults, classical fault models, multiple-coupling faults, Markov chains, integrated circuit testing, Markov processes, random-access storage, RAMs, test patterns, parameters, random-access memories, pattern-sensitive faults, deterministic testing, single faults
38Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi Adapting to intermittent faults in multicore systems. Search on Bibsonomy ASPLOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF overcommitted system, intermittent faults
38Cecilia Metra, Stefano Di Francescantonio, T. M. Mak Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF clock faults, Testing, clock distribution network, manufacturing test
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