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Searching for phrase Full-scan (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1979-1995 (32) 1996-1997 (17) 1998-1999 (20) 2000-2001 (25) 2002 (16) 2003-2004 (29) 2005 (16) 2006-2007 (23) 2008-2009 (17) 2010-2021 (10)
Publication types (Num. hits)
article(68) inproceedings(137)
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The graphs summarize 292 occurrences of 144 keywords

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Found 205 publication records. Showing 205 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
82Elizabeth M. Rudnick, Janak H. Patel A genetic approach to test application time reduction for full scan and partial scan circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
79Subhrajit Bhattacharya, Sujit Dey H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
78Ilker Hamzaoglu, Janak H. Patel Reducing Test Application Time for Full Scan Embedded Cores. Search on Bibsonomy FTCS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF test generation, design-for-testability, fault simulation, embedded cores, full scan
73Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen Cost-free scan: a low-overhead scan path design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
73Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen Cost-free scan: a low-overhead scan path design methodology. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Testing, DFT, Scan design
73Nicola Nicolici, Bashir M. Al-Hashimi Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
68Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy On reducing test application time for scan circuits using limited scan operations and transfer sequences. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
68Dong Xiang, Kaiwei Li, Hideo Fujiwara Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
66Soo Young Lee, Kewal K. Saluja Test application time reduction for sequential circuits with scan. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
61Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita Test sequence compaction by reduced scan shift and retiming. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
58Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Scan forest, test application cost, test data volume, test power
58Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu A cost-effective scan architecture for scan testing with non-scan test power and test application cost. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
52Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier Enhanced Reduced Pin-Count Test for Full-Scan Design. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
51Xiaoding Chen, Michael S. Hsiao An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik Integration of partial scan and built-in self-test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test points, built-in self-test, design for testability, partial scan
48Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li 0036, Krishnendu Chakrabarty Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel Cyclic stress tests for full scan circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
47Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng An almost full-scan BIST solution-higher fault coverage and shorter test application time. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
46Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy Full Scan Fault Coverage With Partial Scan. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
46Seongmoon Wang, Sandeep K. Gupta 0001 An automatic test pattern generator for minimizing switching activity during scan testing activity. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
46Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik On improving test quality of scan-based BIST. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
44Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
44Tsung-Chu Huang, Kuen-Jong Lee An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
43Zhen Chen, Dong Xiang, Boxue Yin A power-effective scan architecture using scan flip-flops clustering and post-generation filling. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF test, low power, design for test, scan design
43Kohei Miyase, Seiji Kajihara Optimal Scan Tree Construction with Test Vector Modification for Test Compression. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Ranganathan Sankaralingam, Nur A. Touba Controlling Peak Power During Scan Testing. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee Test-point insertion: scan paths through functional logic. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
41Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda Scan insertion criteria for low design impact. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
41Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta An RTL methodology to enable low overhead combinational testing. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
39Irith Pomeranz, Sudhakar M. Reddy On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance
39Irith Pomeranz, Sudhakar M. Reddy Reducing test application time for full scan circuits by the addition of transfer sequences. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
38Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Faults in scan cells, stuck-at and stuck-on faults
38Mehdi Salmani Jelodar, Kiarash Mizanian Power Aware Scan-Based Testing using Genetic Algorithm. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita Partial scan design and test sequence generation based on reduced scan shift method. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation
38Prab Varma, Tushar Gheewala The economics of scan-path design for testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs
36Dhiraj K. Pradhan, Jayashree Saxena A novel scheme to reduce test application time in circuits with full scan. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
36Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
36Ching-Hwa Cheng Design Scan Test Strategy for Single Phase Dynamic Circuits. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Irith Pomeranz, Sudhakar M. Reddy Functional Test Generation for Full Scan Circuits. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski Using a software testing technique to identify registers for partial scan implementation. Search on Bibsonomy SBCCI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design
33Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy Synthesis of Scan Chains for Netlist Descriptions at RT-Level. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF scan synthesis, design for testability (DFT), register transfer level (RTL)
33Ranganathan Sankaralingam, Nur A. Touba Inserting Test Points to Control Peak Power During Scan Testing. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya Reducing Power Dissipation during Test Using Scan Chain Disable. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33Robert B. Norwood, Edward J. McCluskey High-Level Synthesis for Orthogonal Sca. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
31Tinne De Laet, Ruben Smits, Joris De Schutter, Herman Bruyninckx Adaptive Full Scan Model for Range Finders in Dynamic Environments. Search on Bibsonomy ISER The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Irith Pomeranz, Sudhakar M. Reddy Static Test Compaction for Multiple Full-Scan Circuits. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Ilker Hamzaoglu, Janak H. Patel Compact two-pattern test set generation for combinational and full scan circuits. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
31Scott Davidson 0001 What's the problem? Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF full-scan test, design for testability, delay test, defects, IC
30Dilip P. Vasudevan, Aristides Efthymiou A Partial Scan Based Test Generation for Asynchronous Circuits. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Jing Wang, Shengbing Zhang, Zhang Meng Testing of a 32-bit High Performance Embedded Microprocessor. Search on Bibsonomy SIES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
28Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Yu Hu 0001, Xiaowei Li 0001, Huawei Li 0001, Xiaoqing Wen Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. Search on Bibsonomy PRDC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Frank te Beest, Ad M. G. Peeters, Kees van Berkel 0001, Hans G. Kerkhoff Synchronous Full-Scan for Asynchronous Handshake Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF L1L2*, DFT, asynchronous circuits, scan design, LSSD
26Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. Search on Bibsonomy ETS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF automatic test pattern generation, scan-based test, high-level testing
26Irith Pomeranz, Sudhakar M. Reddy Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Kwang-Ting Cheng, Chih-Jen Lin Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST. Search on Bibsonomy ITC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
25Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng A Test Synthesis Approach to Reducing BALLAST DFT Overhead. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
24Irith Pomeranz, Sudhakar M. Reddy The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Yu-Chiun Lin, Shi-Yu Huang Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Aiman El-Maleh, Ali Al-Suwaiyan An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
23Irith Pomeranz, Sudhakar M. Reddy Output-Dependent Diagnostic Test Generation. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF diagnostic test generation, stuck-at faults, full-scan circuits
23Scott Davidson 0001 The commonality of vector generation techniques. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF output compression, non-fault-directed test, semi-fault-directed test, ATPG, test compression, full scan, vector generation, logic BIST
23Irith Pomeranz, Sudhakar M. Reddy Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF functional broadside tests, test generation, transition faults, reachable states, full-scan circuits
23Irith Pomeranz, Sudhakar M. Reddy Synthesis for Broadside Testability of Transition Faults. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
23Yong-sheng Cheng, Zhiqiang You, Jishun Kuang Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF full scan testing, scan tree, routing complexity, test response data volume, design-for-testability
23Wang-Dauh Tseng Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF transition density, switching activity during test, clique, low power testing, full scan
23Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero An evolutionary algorithm for reducing integrated-circuit test application time. Search on Bibsonomy SAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF interleaved-scan, test, evolutionary algorithm, computer aided design, full-scan
23Madhu K. Iyer, Kwang-Ting Cheng Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
23Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal A partition and resynthesis approach to testable design of large circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
23Mohamed Soufi, Yvon Savaria, Bozena Kaminska On the design of at-speed testable VLSI circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
23Irith Pomeranz, Sudhakar M. Reddy Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
23Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho Test Power Reduction with Multiple Capture Orders. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Irith Pomeranz, Sudhakar M. Reddy On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states
23Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin Partial-scan delay fault testing of asynchronous circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23Debaditya Mukherjee, Melvin A. Breuer An IEEE 1149.1 Compliant Test Control Architecture. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
23Arun Balakrishnan, Srimat T. Chakradhar Sequential Circuits with combinational Test Generation Complexity. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
23Ajay Khoche, Erik Brunvand Testing self-timed circuits using partial scan. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF sequential network, partial scan environment, logic testing, sequential circuits, asynchronous circuits, partial scan, data paths, self-timed circuits
20Tsung-Chu Huang, Kuen-Jong Lee Reduction of power consumption in scan-based circuits during testapplication by an input control technique. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
20Seongmoon Wang, Sandeep K. Gupta 0001 ATPG for Heat Dissipation Minimization During Scan Testing. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
20Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel Sequential circuit testability enhancement using a nonscan approach. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
18Aristides Efthymiou, John Bainbridge, Douglas A. Edwards Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Themistoklis Haniotakis, Spyros Tragoudas, G. Pani Reduced Test Application Time Based on Reachability Analysis. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang A Study on Insuring the Full Reliability of Finite State Machine. Search on Bibsonomy ICCSA (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
18Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka A SoC Test Strategy Based on a Non-Scan DFT Method. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF non-scan DFT, high level design and test, SoC test
18Debesh K. Das, Bhargab B. Bhattacharya Testable design of non-scan sequential circuits using extra logic. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
18Ajay Khoche, Erik Brunvand A partial scan methodology for testing self-timed circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
16Qidong Wang, Aijiao Cui, Gang Qu 0001 Identification of Counter Registers through Full Scan Chain. Search on Bibsonomy ITC-Asia The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
16Chengkang He, Aijiao Cui, Chip-Hong Chang Identification of State Registers of FSM Through Full Scan by Data Analytics. Search on Bibsonomy AsianHOST The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
16Sylwester Milewski, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada Full-scan LBIST with capture-per-cycle hybrid test points. Search on Bibsonomy ITC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Tinne De Laet, Joris De Schutter, Herman Bruyninckx A Rigorously Bayesian Beam Model and an Adaptive Full Scan Model for Range Finders in Dynamic Environments. Search on Bibsonomy CoRR The full citation details ... 2014 DBLP  BibTeX  RDF
16Irith Pomeranz, Sudhakar M. Reddy Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
16Irith Pomeranz, Sudhakar M. Reddy Static test compaction for diagnostic test sets of full-scan circuits. Search on Bibsonomy IET Comput. Digit. Tech. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
16Irith Pomeranz, Sudhakar M. Reddy On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
16Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
16Davide Appello, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
16Tinne De Laet, Joris De Schutter, Herman Bruyninckx A Rigorously Bayesian Beam Model and an Adaptive Full Scan Model for Range Finders in Dynamic Environments. Search on Bibsonomy J. Artif. Intell. Res. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
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