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Found 2210 publication records. Showing 2210 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
127Yogesh Singh, Anju Saha A Metric-Based Approach to Assess Class Testability. Search on Bibsonomy XP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
112Jeffrey M. Voas, Keith W. Miller 0001 Software Testability: The New Verification. Search on Bibsonomy IEEE Softw. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
110C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal A STAFAN-like functional testability measure for register-level circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
107Jerry Gao 0002, Ming-Chih Shih A Component Testability Model for Verification and Measurement. Search on Bibsonomy COMPSAC (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF component testability, component testing and component-based software testing, testability analysis, testability measurement
107Harry Hengster, Rolf Drechsler, Bernd Becker 0001 On local transformations and path delay fault testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF path delay fault model, testability preserving transformations, testability inproving transformations, design for testability
99Dong Xiang, Yi Xu, Hideo Fujiwara Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF inversion parity, nonscan design for testability, sequential depth for testability, Conflict, testability measure, partial scan design
92Amey Karkare, Manoj Singla, Ajai Jain Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Testability Preserving Transformations, Testability Enhancing Transformations, DFT, Testability, Delay Faults
82Benoit Baudry, Yves Le Traon, Gerson Sunyé, Jean-Marc Jézéquel Measuring and Improving Design Patterns Testability. Search on Bibsonomy IEEE METRICS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
81Alvin Jee, F. Joel Ferguson A methodolgy for characterizing cell testability. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects
80Xinli Gu RT level testability-driven partitioning. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testability-driven partitioning, RT level designs, hard-to-test points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, built-in self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques
78Raees Ahmad Khan, Khurram Mustafa Metric based testability model for object oriented design (MTMOOD). Search on Bibsonomy ACM SIGSOFT Softw. Eng. Notes The full citation details ... 2009 DBLP  DOI  BibTeX  RDF software characteristics, software testability, model, design, object oriented, metrics
78Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang Novel techniques for improving testability analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns
78Antonia Bertolino, Lorenzo Strigini On the Use of Testability Measures for Dependability Assessment. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ultra-high reliability, software testing, error, Bayesian inference, testability, failure, fault, test oracle, reliability assessment
76Frank F. Hsu, Janak H. Patel A distance reduction approach to design for testability. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
76Wuudiann Ke, Premachandran R. Menon Multifault testability of delay-testable circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
76Taghi M. Khoshgoftaar, Robert M. Szabo, Jeffrey M. Voas Detecting program modules with low testability. Search on Bibsonomy ICSM The full citation details ... 1995 DBLP  DOI  BibTeX  RDF aircraft computers, program module detection, low testability, static software product measures, dynamic quality measure, real time avionics software system, component program modules, classification performance, discriminant modeling methodology, real-time systems, software quality, software metrics, program testing, testability, testability analysis, principal components
75Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian Easily Testable Cellular Carry Lookahead Adders. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
74Indradeep Ghosh, Niraj K. Jha, Sujit Dey A low overhead design for testability and test generation technique for core-based systems-on-a-chip. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
73Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test
73Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz LOT: logic optimization with testability-new transformations using recursive learning. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF EX-OR gates, logic optimization with testability, multi-level logic circuits, tstfx, logic design, combinational circuits, logic CAD, gate level, random-pattern testability, recursive learning
72Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
70Nguyen Thanh Binh 0002, Michel Delaunay, Chantal Robach Testability Analysis Applied to Embedded Data-flow Software. Search on Bibsonomy QSIC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Data-flow Software, Software Measurement, Testability Analysis
70Sandhya Seshadri, Michael S. Hsiao Behavioral-Level DFT via Formal Operator Testability Measures. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF behavioral level, operator testability, value range, SSA representation, DFT
70Martin R. Woodward, Zuhoor A. Al-Khanjari Testability, fault size and the domain-to-range ratio: An eternal triangle. Search on Bibsonomy ISSTA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF domain-to-range ratio, fault size, controllability, observability, testability
70Charles E. Stroud, Ahmed E. Barbour Testability and test generation for majority voting fault-tolerant circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults
69Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF strong testability, partially strong testability, complete fault efficiency, design-for-testability, data paths
69Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara Strong self-testability for data paths high-level synthesis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment
69Sujit Dey, Anand Raghunathan, Kenneth D. Wagner Design for Testability Techniques at the Behavioral and Register-Transfer Levels. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
69Yves Le Traon, Chantal Robach Testability analysis of co-designed systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF co-designed data-flow specifications, high level testability analysis, information transfer graph, bipartite directed graph, SATAN tool, computer assisted specification diagram, all-nodes criterion, all-paths criterion, multiple clue strategy, start big strategy, diagnosis quality factor, software components testability, formal specification, fault diagnosis, program testing, data flow analysis, computer aided software engineering, hardware description languages, data flow graphs, testability analysis, automatic test software, functional specification, test set generation, avionics systems, hardware modelling
67Josef Strnadel TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
67Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
67Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza ALADIN: a multilevel testability analyzer for VLSI system design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
66Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel Enhancing high-level control-flow for improved testability. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description
66Kee Sup Kim, Charles R. Kime Partial scan flip-flop selection by use of empirical testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scan flip-flop selection, serial scan, design for testability, testability, partial scan
64Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. Search on Bibsonomy ISMVL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM
62Laurence Tianruo Yang, Zebo Peng Incremental Testability Analysis for Partial Scan Selection and Design Transformations. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF incremental testability analysis, partial scan selection, design transformation, register transfer level, high-level test synthesis
62Pu-Lin Yeh, Jin-Cherng Lin Software Testability Measurements Derived from Data Flow Analysis. Search on Bibsonomy CSMR The full citation details ... 1998 DBLP  DOI  BibTeX  RDF software testability, software testing, software measurement, data flow, testing criteria
62Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Respecification, Synthesis for Testability, Don't Cares, High Level Testing
62Jeffrey M. Voas Software testability measurement for intelligent assertion placement. Search on Bibsonomy Softw. Qual. J. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF testing, observability, testability, failure, fault, assertions, fault propagation
62Prashant S. Parikh, Miron Abramovici Testability-based partial scan analysis. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testability cost, sensitivity analysis, partial scan
61Hiroaki Ueda, Kozo Kinoshita Low power design and its testability. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
61Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
59Tsung-Han Tsai, Chin-Yu Huang, Jun-Ru Chang A Study of Applying Extended PIE Technique to Software Testability Analysis. Search on Bibsonomy COMPSAC (1) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
59Dong Xiang, Shan Gu, Hideo Fujiwara Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
59Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
59Sandeep Bhatia, Niraj K. Jha Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
58Tomokazu Yoneda, Hideo Fujiwara Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability
58Tomokazu Yoneda, Hideo Fujiwara A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF consecutive transparency, core-based systems-on-a-chip, design for testability, test access mechanism, consecutive testability
58Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara Single-control testability of RTL data paths for BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
58Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker 0001 Testability of 2-Level AND/EXOR Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF AND/EXOR, 2-level circuits, synthesis for testability, random pattern testability
58Giacomo Buonanno, Franco Fummi, Donatella Sciuto TIES: A testability increase expert system for VLSI design. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF design for testability techniques, DfT advisor, testability analysis, testable design
58João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves A methodology for testability enhancement at layout level. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF physical design rules for testability, simulation, fault modeling, testability analysis
55Smita Krishnaswamy, Igor L. Markov, John P. Hayes Improving testability and soft-error resilience through retiming. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF testability, soft errors, retiming
55George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing
55Ronny Kolb, Dirk Muthig Making testing product lines more efficient by improving the testability of product line architectures. Search on Bibsonomy ROSATEA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF evaluation, design, architecture, testing, software product line, testability
55Jaan Raik, Tanel Nõmmeots, Raimund Ubar A New Testability Calculation Method to Guide RTL Test Generation. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF test pattern generation, register-transfer level, decision diagrams, testability measures
55Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing
55Kelly A. Ockunzzi, Christos A. Papachristou Testability Enhancement for Control-Flow Intensive Behaviors. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF behavioral testability analysis and insertion, BIST, test synthesis
55Zdenek Kotásek, F. Zboril RT level testability analysis to reduce test application time. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction
55Harry Hengster, Rolf Drechsler, Bernd Becker 0001 On the application of local circuit transformations with special emphasis on path delay fault testability. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF local circuit transformations, path delay fault testability, SALT, logic testing, delays, integrated circuit testing, automatic testing
55Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja Incorporating testability considerations in high-level synthesis. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
54Franco Fummi, Donatella Sciuto, M. Serro Synthesis for testability of large complexity controllers. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
53Sandhya Seshadri, Michael S. Hsiao Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF behavioral level, value range, SSA representation, design for testability
51Irith Pomeranz, Sudhakar M. Reddy Synthesis for Broadside Testability of Transition Faults. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
51Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina Testability Estimation Based on Controllability and Observability Parameters. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
51Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang Design-for-testability and fault-tolerant techniques for FFT processors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
51Dong Xiang, Shan Gu, Hideo Fujiwara Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
51Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha TAO: regular expression-based register-transfer level testability analysis and optimization. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
51A. N. Trahtman Piecewise and Local Threshold Testability of DFA. Search on Bibsonomy FCT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF locally threshold testable, piecewise testable, locally testable, syntactic semigroup, algorithm, automaton, transition graph
51Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang TAIR: testability analysis by implication reasoning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
51Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz LOT: Logic Optimization with Testability. New transformations for logic synthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
51Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF controller resynthesis, test synthesis, high-level testing
51Hingsam S. Fung, Sanford Hirschhorn, R. Kulkarni Design for testability in a silicon compilation environment. Search on Bibsonomy DAC The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
50Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF design for testability, system-on-a-chip, test scheduling, test access mechanism, consecutive testability
50Frank F. Hsu, Janak H. Patel Design for Testability Using State Distances. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF state distance, finite-state-machine, design-for-testability, synthesis-for-testability
50Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel Testability Insertion in Behavioral Descriptions. Search on Bibsonomy ISSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description
50Yu Fang, Alexander Albicki Efficient testability enhancement for combinational circuit. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
50Chunduri Rama Mohan, Partha Pratim Chakrabarti Combined optimization of area and testability during state assignment of PLA-based FSM's. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
50Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar Testability-oriented channel routing. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield
50Fabrizio Lombardi, Donatella Sciuto Constant testability of combinational cellular tree structures. Search on Bibsonomy J. Electron. Test. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF Constant testability, testing, design for testability, finite automata, tree structures
47Phil McMinn Search-based failure discovery using testability transformations to generate pseudo-oracles. Search on Bibsonomy GECCO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF non-testable program, pseudo-oracle, search-based software testing, testability transformation, program transformation, oracle
47Misko Hevery Testability explorer: using byte-code analysis to engineer lasting social changes in an organization's software development process. Search on Bibsonomy OOPSLA Companion The full citation details ... 2008 DBLP  DOI  BibTeX  RDF byte-code analysis, refactoring, unit testing, testability, social engineering
47Michel Jaring, René L. Krikhaar, Jan Bosch Modeling Variability and Testability Interaction in Software Product Line Engineering. Search on Bibsonomy ICCBSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF software product line, variability, testability
47Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen A Statistic-Based Approach to Testability Analysis. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF fault detection probability, controllability, observability, Testability analysis
47Lian Yu, Lifeng Xu, Guanzhu Wang, Chang Yan Chi, Wenping Xiao, Hui Su Testability and Test Framework for Collaborative Real-Time Editing Tools. Search on Bibsonomy QSIC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF timeline diagram, grey-box testing, visualization, collaboration, testability, test framework
47Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Testing of embedded systems, VHDL, ATPG, fault modeling, testability analysis
47Zuhoor A. Al-Khanjari, Martin R. Woodward, Haider Ali Ramadhan Critical Analysis of the PIE Testability Technique. Search on Bibsonomy Softw. Qual. J. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF PIE technique, mutant schemata, testability, sensitivity, infection
47Nguyen Thanh Binh 0002, Michel Delaunay, Chantal Robach Testability Analysis for Software Components. Search on Bibsonomy ICSM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Data-flow Systems, Software Metrics, Testability Analysis, Testing Criteria
47Harry Hengster, Bernd Becker 0001 Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability. Search on Bibsonomy FTCS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits
47Kamel Karoui, Abderrazak Ghedamsi, Rachida Dssouli A Study of Some Influencing Factors in Testability and Diagnostics Based on FSMs. Search on Bibsonomy ISCC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Design, Controllability, Abstraction, Fuzziness, Testability, Diagnostics, Distinguishability
47Kowen Lai, Christos A. Papachristou, Mikhail Baklashov BIST testability enhancement using high level test synthesis for behavioral and structural designs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF BIST testability, behavioral designs, industrial benchmark, controllability, built-in self test, observability, DFT, transparency, fidelity, structural designs, high level test synthesis
47Marc Perbost, Ludovic Le Lan, Christian Landrault Automatic Testability Analysis of Boards and MCMs at Chip Level. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF DFT, testability analysis, MCM
47Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz On minimizing the number of test points needed to achieve complete robust path delay fault testability. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion
47Johannes Steensma, Werner Geurts, Francky Catthoor, Hugo De Man Testability analysis in high level data path synthesis. Search on Bibsonomy J. Electron. Test. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Data path testing, high level synthesis, test pattern generation, testability analysis
46Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
46Srivaths Ravi 0001, Niraj K. Jha Test synthesis of systems-on-a-chip. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
46Frank F. Hsu, Janak H. Patel High-Level Controllability and Observability Analysis for Test Synthesis. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF controllability, observability, high-level test synthesis, behavioral modification
46Christos A. Papachristou, Mikhail Baklashov, Kowen Lai High-Level Test Synthesis for Behavioral and Structural Designs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF built-in self test, DFT, test synthesis
44Dong Xiang, Janak H. Patel Partial Scan Design Based on Circuit State Information and Functional Analysis. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Valid state, invalid state, testability improvement potential, conflict, testability measure, partial scan design
44Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki Cost/Quality Trade-off in Synthesis for BIST. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF DFT reuse, BIST, synthesis for testability, testability analysis
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