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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10002 occurrences of 3019 keywords
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Results
Found 11893 publication records. Showing 11893 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | Wei-lun Kao, Ravishankar K. Iyer, Dong Tang |
FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior under Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 19(11), pp. 1105-1118, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
FINE, fault injection and monitoring environment, UNIX system behavior, hardware-induced software errors, fault injector, analysis utilities, SunOS 4.1.2, transient Markov reward analysis, bus faults, CPU faults, pointer faults, software tools, Unix, program testing, system monitoring, software faults, software monitor, workload generator |
92 | Bin Liu, Fabrizio Lombardi, Wei-Kang Huang |
Testing programmable interconnect systems: an algorithmic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 311-316, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits |
84 | Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell |
Functional test generation for path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 339-345, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults |
74 | Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck |
Deterministic test generation for non-classical faults on the gate level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 244-251, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST |
72 | Irith Pomeranz, Sudhakar M. Reddy |
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2219-2227, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
On the characterization and efficient computation of hard-to-detect bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1640-1649, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
63 | Bruce F. Cockburn, Janusz A. Brzozowski |
Near-optimal tests for classes of write-triggered coupling faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(3), pp. 251-264, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
toggling faults, lower bounds, coupling faults, RAM testing, optimal tests |
62 | Irith Pomeranz, Sudhakar M. Reddy |
On achieving complete fault coverage for sequential machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3), pp. 378-386, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
59 | Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar |
Primitive delay faults: identification, testing, and design for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), pp. 669-684, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
58 | Michiel M. Ligthart, Rudi J. Stans |
A fault model for PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(2), pp. 265-270, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
58 | Irith Pomeranz, Sudhakar M. Reddy |
Partitioned n-detection test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 93-98, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets |
57 | João Durães, Henrique Madeira |
Emulation of Software Faults: A Field Data Study and a Practical Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 32(11), pp. 849-867, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
software reliability, Fault injection, software faults |
57 | Amitabha Bagchi, Ankur Bhargava, Amitabh Chaudhary, David Eppstein, Christian Scheideler |
The effect of faults on network expansion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 27-30, 2004, Barcelona, Spain, pp. 286-293, 2004, ACM, 1-58113-840-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
d-dimensional mesh, faulty networks, expansion, random faults |
57 | Mark C. Hansen, John P. Hayes |
High-level test generation using physically-induced faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 20-28, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test |
57 | Yashwant K. Malaiya, Stephen Y. H. Su |
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(8), pp. 600-604, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
modeling of faults, Markov model, transient faults, multiple faults, fault-tolerant system, reliability analysis, intermittent faults, permanent faults, Fault-tolerant design, reliability evaluation, reconfiguration scheme, hardware redundancy |
55 | Kwang-Ting Cheng, Hsi-Chuan Chen |
Classification and identification of nonrobust untestable path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8), pp. 845-853, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
55 | Petru Cascaval, Stuart Bennett, Corneliu Hutanu |
Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 227-243, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fault simulation, memory testing, march test, coupling faults, functional faults |
55 | Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik |
March LR: a test for realistic linked faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 272-280, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults |
54 | Tomislav Lovric |
Systematic and Design Diversity - Software Techniques for Hardware Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-1, First European Dependable Computing Conference, Berlin, Germany, October 4-6, 1994, Proceedings, pp. 309-326, 1994, Springer, 3-540-58426-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
design faults, operational faults, fault detection coverage, relative test, absolute test, software implemented hardware-fault injection, systematic diversity, Virtual Duplex System, self-checking, design diversity, fail-safe |
53 | Thomas J. Ostrand, Elaine J. Weyuker, Robert M. Bell |
Predicting the Location and Number of Faults in Large Software Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 31(4), pp. 340-355, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
software testing, prediction, empirical study, Software faults, regression model, fault-prone |
53 | Olivier Contant, Stéphane Lafortune, Demosthenis Teneketzis |
Diagnosis of Intermittent Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Event Dyn. Syst. ![In: Discret. Event Dyn. Syst. 14(2), pp. 171-202, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fault diagnosis, fault detection, diagnosability, intermittent faults |
53 | Henrique Madeira, Diamantino Costa, Marco Vieira |
On the Emulation of Software Faults by Software Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 25-28 June 2000, New York, NY, USA, pp. 417-426, 2000, IEEE Computer Society, 0-7695-0707-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fault injection, software faults, fault classification |
53 | Subhachandra Chandra, Peter M. Chen |
Whither Generic Recovery from Application Faults? A Fault Study using Open-Source Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 25-28 June 2000, New York, NY, USA, pp. 97-106, 2000, IEEE Computer Society, 0-7695-0707-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Heisenbugs, Software, Recovery, Faults, Transient |
53 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 560-574, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults |
52 | Udo Mahlstedt, Jürgen Alt, Matthias Heinitz |
CURRENT: a test generation system for IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 317-323, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults |
52 | V. Kim, T. Chen |
Assessing SRAM test coverage for sub-micron CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 24-30, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits |
51 | Charles J. Colbourn, Daniel W. McClary |
Locating and detecting arrays for interaction faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Optim. ![In: J. Comb. Optim. 15(1), pp. 17-48, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Disjunct matrix, Locating array, Defecting array, Covering array, Orthogonal array, Cover-free family, Factorial design |
51 | Hyunsook Do, Gregg Rothermel |
On the Use of Mutation Faults in Empirical Assessments of Test Case Prioritization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 32(9), pp. 733-752, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
program mutation, empirical studies, Regression testing, test case prioritization |
51 | Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen |
Identification of robust untestable path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 229-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification |
51 | Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara |
Compact test generation for bridging faults under IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 310-316, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing |
51 | Bruce F. Cockburn |
Deterministic tests for detecting singleV-coupling faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 91-113, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
V-coupling faults, lower bounds, Functional tests, pattern-sensitive faults, RAM testing |
51 | El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny |
On the generation of test patterns for multiple faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(3), pp. 237-253, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis |
50 | David Walker 0001, Lester W. Mackey, Jay Ligatti, George A. Reis, David I. August |
Static typing for a faulty lambda calculus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFP ![In: Proceedings of the 11th ACM SIGPLAN International Conference on Functional Programming, ICFP 2006, Portland, Oregon, USA, September 16-21, 2006, pp. 38-49, 2006, ACM, 1-59593-309-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transient hardware faults, fault tolerance, type systems, lambda calculus, reliable computing, typed intermediate languages, soft faults |
49 | Irith Pomeranz, Sudhakar M. Reddy |
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(4), pp. 491-495, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance |
49 | Norman E. Fenton, Niclas Ohlsson |
Quantitative Analysis of Faults and Failures in a Complex Software System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 26(8), pp. 797-814, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Software faults and failures, empirical studies, software metrics |
49 | Srikanth Venkataraman, W. Kent Fuchs |
A deductive technique for diagnosis of bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 562-567, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Diagnosis, Bridging faults, Deduction |
49 | Jack R. Smith, Tian Xia, Charles E. Stroud |
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(3), pp. 239-253, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
stuck-at faults, bridging faults, delay faults |
49 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 344-353, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
48 | Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki |
Experimental fault analysis of 1 Mb SRAM chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 31-36, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips |
48 | Kuo-Chung Tai |
Theory of Fault-Based Predicate Testing for Computer Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 22(8), pp. 552-562, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
predicate testing, boolean operator faults, relational operator faults, off-by-$epsilon$ faults, Software testing, fault-based testing |
48 | K. Vijayananda |
Distributed fault detection in communication protocols using extended finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 310-318, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines |
48 | Andrej Zemva, Franc Brglez |
Detectable perturbations: a paradigm for technology-specific multi-fault test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 350-357, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system |
48 | Jan Schat |
Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 235-240, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Joaquin Gracia, Luis J. Saiz, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil |
Analysis of the influence of intermittent faults in a microcontroller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 80-85, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Hyunsook Do, Gregg Rothermel |
A Controlled Experiment Assessing Test Case Prioritization Techniques via Mutation Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 21st IEEE International Conference on Software Maintenance (ICSM 2005), 25-30 September 2005, Budapest, Hungary, pp. 411-420, 2005, IEEE Computer Society, 0-7695-2368-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
48 | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
On the Characterization of Hard-to-Detect Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11012-11019, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee |
Analog circuit equivalent faults in the D.C. domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 84-89, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits |
47 | Irith Pomeranz, Sudhakar M. Reddy |
Classification of Faults in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(9), pp. 1066-1077, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
undetectable faults, initial conditions, partially detectable faults, synchronization mode, free mode, logic testing, sequential circuits, synchronisation, fault location, synchronous sequential circuits, combinatorial circuits, test sequence, faults classification, redundant faults |
46 | Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren |
Quantitative Analysis of In-Field Defects in Image Sensor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 526-534, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Sandeep S. Kulkarni, Ali Ebnenasir |
Automated Synthesis of Multitolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June - 1 July 2004, Florence, Italy, Proceedings, pp. 209-, 2004, IEEE Computer Society, 0-7695-2052-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Fault-tolerance, Formal methods, Distributed programs, Program synthesis, Automatic addition of fault-tolerance |
46 | Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
A circuit level fault model for resistive bridges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 546-559, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fault models, bridge faults, delay faults |
46 | Samy Makar, Edward J. McCluskey |
Checking experiments to test latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 196-201, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults |
46 | Said Hamdioui, Ad J. van de Goor |
Efficient Tests for Realistic Faults in Dual-Port SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(5), pp. 460-473, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Multiport/single-port memories, weak faults, fault models, fault coverage, march tests |
46 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 55-67, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
digital circuit testing, test generation, fault models, delay test, path delay faults |
46 | Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour |
Diagnosing multiple transition faults in the absence of timing information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 193-196, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
diagnosis, multiple faults, delay faults, incremental, transition faults |
45 | Irith Pomeranz, Sudhakar M. Reddy |
Test enrichment for path delay faults using multiple sets of target faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1), pp. 82-90, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara |
Single-control testability of RTL data paths for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 210-215, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test |
44 | Bo Yao, Irith Pomeranz, Sudhakar M. Reddy |
Deterministic broadside test generation for transition path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 135-138, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
broadside test, deterministic test generation, path delay fault, transition fault |
44 | Sultan M. Al-Harbi, Fadel Noor, Fadi M. Al-Turjman |
March DSS: A New Diagnostic March Test for All Memory Simple Static Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1713-1720, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Abhishek B. Sharma, Leana Golubchik, Ramesh Govindan |
On the Prevalence of Sensor Faults in Real-World Deployments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SECON ![In: Proceedings of the Fourth Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks, SECON 2007, Merged with IEEE International Workshop on Wireless Ad-hoc and Sensor Networks (IWWAN), June 18-21, 2007, San Diego, California, USA, pp. 213-222, 2007, IEEE, 1-4244-1268-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Man Fai Lau, Ying Liu, Yuen-Tak Yu |
Detecting Double Faults on Term and Literal in Boolean Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QSIC ![In: Seventh International Conference on Quality Software (QSIC 2007), 11-12 October 2007, Portland, Oregon, USA, pp. 117-126, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Evangelos Kranakis, Michel Paquette, Andrzej Pelc |
Communication in Networks with Random Dependent Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 2007, 32nd International Symposium, MFCS 2007, Ceský Krumlov, Czech Republic, August 26-31, 2007, Proceedings, pp. 418-429, 2007, Springer, 978-3-540-74455-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dependent faults, crash faults, Fault-tolerance, communication, network connectivity |
44 | József Sziray |
Test Calculation for Logic and Delay Faults in Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA, pp. 20-32, 2006, IEEE Computer Society, 978-0-7695-2839-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic |
44 | Ramesh C. Tekumalla, Premachandran R. Menon |
On Redundant Path Delay Faults in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 277-282, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
functional sensitizability, sequential circuits, testability, Path delay faults, redundant faults |
44 | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana |
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 545-546, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults |
44 | Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Compact and complete test set generation for multiple stuck-faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 212-219, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Multiple stuck faults, complete test set generation, irrepressible faults |
42 | James H. Andrews, Lionel C. Briand, Yvan Labiche |
Is mutation an appropriate tool for testing experiments? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 27th International Conference on Software Engineering (ICSE 2005), 15-21 May 2005, St. Louis, Missouri, USA, pp. 402-411, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hand-seeded faults, mutants, real faults |
42 | Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor |
Memory Fault Modeling Trends: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 245-255, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
static faults, fault models, fault coverage, memory tests, dynamic faults, data backgrounds |
42 | Zaid Al-Ars, Ad J. van de Goor |
Modeling Techniques and Tests for Partial Faults in Memory Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 89-93, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
partial faults, completing operations, fault models, memory testing, DRAMs, defect simulation |
42 | Ulrich Schmid 0001, Bettina Weiss, John M. Rushby |
Formally Verified Byzantine Agreement in Presence of Link Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: Proceedings of the 22nd International Conference on Distributed Computing Systems (ICDCS'02), Vienna, Austria, July 2-5, 2002, pp. 608-616, 2002, IEEE Computer Society, 0-7695-1585-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
assumption coverage, formal verification, lower bounds, fault models, consensus, Byzantine agreement, Fault-tolerant distributed systems, link faults, impossibility results |
40 | Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji |
Modified Stability Checking for On-line Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 787-792, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
crosstalk faults and transient faults, SEU testing, modified stability checking, delay faults, self-checking circuits, Concurrent testing, on-line error detection |
40 | Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy |
Fsimac: a fault simulator for asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 114-119, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits |
40 | Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve |
Accurate microarchitecture-level fault modeling for studying hardware faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 105-116, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Man Fai Lau, Ying Liu, Yuen-Tak Yu |
On Detection Conditions of Double Faults Related to Terms in Boolean Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC (1) ![In: 30th Annual International Computer Software and Applications Conference, COMPSAC 2006, Chicago, Illinois, USA, September 17-21, 2006. Volume 1, pp. 403-410, 2006, IEEE Computer Society, 0-7695-2655-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy |
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 294-299, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Irith Pomeranz, Sudhakar M. Reddy |
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2), pp. 288-294, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Joakim Aidemark, Peter Folkesson, Johan Karlsson |
On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 68-74, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Sultan M. Al-Harbi, Sandeep K. Gupta 0001 |
Generating Complete and Optimal March Tests for Linked Faults in Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 254-266, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | João Durães, Henrique Madeira |
Emulation of Software Faults by Educated Mutations at Machine-Code Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 13th International Symposium on Software Reliability Engineering (ISSRE 2002), 12-15 November 2002, Annapolis, MD, USA, pp. 329-340, 2002, IEEE Computer Society, 0-7695-1763-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Xiaoding Chen, Michael S. Hsiao |
Characteristic faults and spectral information for logic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 294-298, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu |
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 16-18 December 2002, Tsukuba-City, Ibarski, Japan, pp. 275-282, 2002, IEEE Computer Society, 0-7695-1852-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Piotr R. Sidorowicz |
Modeling and Testing Transistor Faults in Content-Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 83-90, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu |
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 64-69, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
Fast identification of untestable delay faults using implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 642-647, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | Irith Pomeranz, Sudhakar M. Reddy |
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 20-25, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | A. Jefferson Offutt, Jane Huffman Hayes |
A Semantic Model of Program Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the 1996 International Symposium on Software Testing and Analysis, ISSTA 1996, San Diego, CA, USA, January 8-10, 1996, pp. 195-200, 1996, ACM, 0-89791-787-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
40 | Nicola Santoro, Peter Widmayer |
Distributed Function Evaluation in the Presence of Transmission Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGAL International Symposium on Algorithms ![In: Algorithms, International Symposium SIGAL '90, Tokyo, Japan, August 16-18, 1990, Proceedings, pp. 358-367, 1990, Springer, 3-540-52921-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
40 | Niraj K. Jha, Qiao Tong |
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 350-354, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
40 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 79-84, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Faults in scan cells, stuck-at and stuck-on faults |
40 | Joonhwan Yi, John P. Hayes |
The Coupling Model for Function and Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(6), pp. 631-649, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test generation, fault modeling, delay faults, functional faults |
40 | Toshiyuki Maeda, Kozo Kinoshita |
Memory reduction of IDDQ test compaction for internal and external bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 350-355, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction |
40 | Kuen-Jong Lee, Jing-Jou Tang |
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 165-171, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits |
40 | Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai |
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 100-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits |
40 | Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham |
A novel test generation approach for parametric faults in linear analog circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 470-475, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits |
40 | Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |
Diagnostic of path and gate delay faults in non-scan sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 380-386, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults |
39 | Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre |
Fault Collapsing via Functional Dominance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 274-280, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara |
A class of sequential circuits with combinational test generation complexity under single-fault assumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 398-403, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault |
38 | René David, Antoine Fuentes, Bernard Courtois |
Random Pattern Testing Versus Deterministic Testing of RAM's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(5), pp. 637-650, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
random pattern testing, double faults, classical fault models, multiple-coupling faults, Markov chains, integrated circuit testing, Markov processes, random-access storage, RAMs, test patterns, parameters, random-access memories, pattern-sensitive faults, deterministic testing, single faults |
38 | Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi |
Adapting to intermittent faults in multicore systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 255-264, 2008, ACM, 978-1-59593-958-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
overcommitted system, intermittent faults |
38 | Cecilia Metra, Stefano Di Francescantonio, T. M. Mak |
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(5), pp. 531-546, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clock faults, Testing, clock distribution network, manufacturing test |
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