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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2833 occurrences of 878 keywords
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Results
Found 2210 publication records. Showing 2210 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
127 | Yogesh Singh, Anju Saha |
A Metric-Based Approach to Assess Class Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
XP ![In: Agile Processes in Software Engineering and Extreme Programming, 9th International Conference, XP 2008, Limerick, Ireland, June 10-14, 2008. Proceedings, pp. 224-225, 2008, Springer, 978-3-540-68254-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
112 | Jeffrey M. Voas, Keith W. Miller 0001 |
Software Testability: The New Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Softw. ![In: IEEE Softw. 12(3), pp. 17-28, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
110 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 192-198, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
107 | Jerry Gao 0002, Ming-Chih Shih |
A Component Testability Model for Verification and Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC (2) ![In: 29th Annual International Computer Software and Applications Conference, COMPSAC 2005, Edinburgh, Scotland, UK, July 25-28, 2005. Volume 2, pp. 211-218, 2005, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
component testability, component testing and component-based software testing, testability analysis, testability measurement |
107 | Harry Hengster, Rolf Drechsler, Bernd Becker 0001 |
On local transformations and path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(3), pp. 173-191, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
path delay fault model, testability preserving transformations, testability inproving transformations, design for testability |
99 | Dong Xiang, Yi Xu, Hideo Fujiwara |
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(8), pp. 1063-1075, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
inversion parity, nonscan design for testability, sequential depth for testability, Conflict, testability measure, partial scan design |
92 | Amey Karkare, Manoj Singla, Ajai Jain |
Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 370-373, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Testability Preserving Transformations, Testability Enhancing Transformations, DFT, Testability, Delay Faults |
82 | Benoit Baudry, Yves Le Traon, Gerson Sunyé, Jean-Marc Jézéquel |
Measuring and Improving Design Patterns Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE METRICS ![In: 9th IEEE International Software Metrics Symposium (METRICS 2003), 3-5 September 2003, Sydney, Australia, pp. 50-, 2003, IEEE Computer Society, 0-7695-1987-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
81 | Alvin Jee, F. Joel Ferguson |
A methodolgy for characterizing cell testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 384-390, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects |
80 | Xinli Gu |
RT level testability-driven partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 176-183, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testability-driven partitioning, RT level designs, hard-to-test points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, built-in self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques |
78 | Raees Ahmad Khan, Khurram Mustafa |
Metric based testability model for object oriented design (MTMOOD). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGSOFT Softw. Eng. Notes ![In: ACM SIGSOFT Softw. Eng. Notes 34(2), pp. 1-6, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
software characteristics, software testability, model, design, object oriented, metrics |
78 | Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang |
Novel techniques for improving testability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 392-397, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns |
78 | Antonia Bertolino, Lorenzo Strigini |
On the Use of Testability Measures for Dependability Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 22(2), pp. 97-108, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ultra-high reliability, software testing, error, Bayesian inference, testability, failure, fault, test oracle, reliability assessment |
76 | Frank F. Hsu, Janak H. Patel |
A distance reduction approach to design for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 158-163, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques |
76 | Wuudiann Ke, Premachandran R. Menon |
Multifault testability of delay-testable circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 400-409, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits |
76 | Taghi M. Khoshgoftaar, Robert M. Szabo, Jeffrey M. Voas |
Detecting program modules with low testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: Proceedings of the International Conference on Software Maintenance, ICSM 1995, Opio (Nice), France, October 17-20, 1995, pp. 242-250, 1995, IEEE Computer Society, 0-8186-7141-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
aircraft computers, program module detection, low testability, static software product measures, dynamic quality measure, real time avionics software system, component program modules, classification performance, discriminant modeling methodology, real-time systems, software quality, software metrics, program testing, testability, testability analysis, principal components |
75 | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
Easily Testable Cellular Carry Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 285-298, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model |
74 | Indradeep Ghosh, Niraj K. Jha, Sujit Dey |
A low overhead design for testability and test generation technique for core-based systems-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11), pp. 1661-1676, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
73 | Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara |
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 313-318, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test |
73 | Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz |
LOT: logic optimization with testability-new transformations using recursive learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 318-325, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
EX-OR gates, logic optimization with testability, multi-level logic circuits, tstfx, logic design, combinational circuits, logic CAD, gate level, random-pattern testability, recursive learning |
72 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 171-176, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions |
70 | Nguyen Thanh Binh 0002, Michel Delaunay, Chantal Robach |
Testability Analysis Applied to Embedded Data-flow Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QSIC ![In: 3rd International Conference on Quality Software (QSIC 2003), 6-7 November 2003, Dallas, TX, USA, pp. 351-, 2003, IEEE Computer Society, 0-7695-2015-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Data-flow Software, Software Measurement, Testability Analysis |
70 | Sandhya Seshadri, Michael S. Hsiao |
Behavioral-Level DFT via Formal Operator Testability Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(6), pp. 595-611, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
behavioral level, operator testability, value range, SSA representation, DFT |
70 | Martin R. Woodward, Zuhoor A. Al-Khanjari |
Testability, fault size and the domain-to-range ratio: An eternal triangle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the International Symposium on Software Testing and Analysis, ISSTA 2000, Portland, OR, USA, August 21-24, 2000, pp. 168-172, 2000, ACM, 1-58113-266-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
domain-to-range ratio, fault size, controllability, observability, testability |
70 | Charles E. Stroud, Ahmed E. Barbour |
Testability and test generation for majority voting fault-tolerant circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(3), pp. 201-214, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults |
69 | Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara |
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 306-311, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
strong testability, partially strong testability, complete fault efficiency, design-for-testability, data paths |
69 | Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara |
Strong self-testability for data paths high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 229-234, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment |
69 | Sujit Dey, Anand Raghunathan, Kenneth D. Wagner |
Design for Testability Techniques at the Behavioral and Register-Transfer Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 79-91, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability |
69 | Yves Le Traon, Chantal Robach |
Testability analysis of co-designed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 206-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
co-designed data-flow specifications, high level testability analysis, information transfer graph, bipartite directed graph, SATAN tool, computer assisted specification diagram, all-nodes criterion, all-paths criterion, multiple clue strategy, start big strategy, diagnosis quality factor, software components testability, formal specification, fault diagnosis, program testing, data flow analysis, computer aided software engineering, hardware description languages, data flow graphs, testability analysis, automatic test software, functional specification, test set generation, avionics systems, hardware modelling |
67 | Josef Strnadel |
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 865-872, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
67 | Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin |
Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 256-259, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
67 | Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza |
ALADIN: a multilevel testability analyzer for VLSI system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(2), pp. 157-171, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
66 | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
Enhancing high-level control-flow for improved testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 322-328, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description |
66 | Kee Sup Kim, Charles R. Kime |
Partial scan flip-flop selection by use of empirical testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 47-59, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scan flip-flop selection, serial scan, design for testability, testability, partial scan |
64 | Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui |
PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 149-155, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM |
62 | Laurence Tianruo Yang, Zebo Peng |
Incremental Testability Analysis for Partial Scan Selection and Design Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 103-113, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
incremental testability analysis, partial scan selection, design transformation, register transfer level, high-level test synthesis |
62 | Pu-Lin Yeh, Jin-Cherng Lin |
Software Testability Measurements Derived from Data Flow Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSMR ![In: 2nd Euromicro Conference on Software Maintenance and Reengineering (CSMR '98), 8-11 March 1998, Florence, Italy, pp. 96-103, 1998, IEEE Computer Society, 0-8186-8421-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
software testability, software testing, software measurement, data flow, testing criteria |
62 | Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 193-198, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Respecification, Synthesis for Testability, Don't Cares, High Level Testing |
62 | Jeffrey M. Voas |
Software testability measurement for intelligent assertion placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 6(4), pp. 327-336, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
testing, observability, testability, failure, fault, assertions, fault propagation |
62 | Prashant S. Parikh, Miron Abramovici |
Testability-based partial scan analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 61-70, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testability cost, sensitivity analysis, partial scan |
61 | Hiroaki Ueda, Kozo Kinoshita |
Low power design and its testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 361-366, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability |
61 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 173-179, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits |
59 | Tsung-Han Tsai, Chin-Yu Huang, Jun-Ru Chang |
A Study of Applying Extended PIE Technique to Software Testability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC (1) ![In: Proceedings of the 33rd Annual IEEE International Computer Software and Applications Conference, COMPSAC 2009, Seattle, Washington, USA, July 20-24, 2009. Volume 1, pp. 89-98, 2009, IEEE Computer Society, 978-0-7695-3726-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
59 | Dong Xiang, Shan Gu, Hideo Fujiwara |
Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 86-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
59 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9), pp. 1001-1014, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
59 | Sandeep Bhatia, Niraj K. Jha |
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2), pp. 228-243, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
58 | Tomokazu Yoneda, Hideo Fujiwara |
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 487-501, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability |
58 | Tomokazu Yoneda, Hideo Fujiwara |
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 193-198, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
consecutive transparency, core-based systems-on-a-chip, design for testability, test access mechanism, consecutive testability |
58 | Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara |
Single-control testability of RTL data paths for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 210-215, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test |
58 | Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker 0001 |
Testability of 2-Level AND/EXOR Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 219-225, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
AND/EXOR, 2-level circuits, synthesis for testability, random pattern testability |
58 | Giacomo Buonanno, Franco Fummi, Donatella Sciuto |
TIES: A testability increase expert system for VLSI design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 203-217, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design for testability techniques, DfT advisor, testability analysis, testable design |
58 | João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves |
A methodology for testability enhancement at layout level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(4), pp. 287-299, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
physical design rules for testability, simulation, fault modeling, testability analysis |
55 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
Improving testability and soft-error resilience through retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 508-513, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
testability, soft errors, retiming |
55 | George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(11), pp. 1449-1457, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing |
55 | Ronny Kolb, Dirk Muthig |
Making testing product lines more efficient by improving the testability of product line architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ROSATEA ![In: Proceedings of the 2006 Workshop on Role of Software Architecture for Testing and Analysis, held in conjunction with the ACM SIGSOFT International Symposium on Software Testing and Analysis (ISSTA 2006), ROSATEA 2006, Portland, Maine, USA, July 17-20, 2006, pp. 22-27, 2006, ACM, 1-59593-459-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
evaluation, design, architecture, testing, software product line, testability |
55 | Jaan Raik, Tanel Nõmmeots, Raimund Ubar |
A New Testability Calculation Method to Guide RTL Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 71-82, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test pattern generation, register-transfer level, decision diagrams, testability measures |
55 | Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee |
A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 361-368, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing |
55 | Kelly A. Ockunzzi, Christos A. Papachristou |
Testability Enhancement for Control-Flow Intensive Behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(3), pp. 239-257, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
behavioral testability analysis and insertion, BIST, test synthesis |
55 | Zdenek Kotásek, F. Zboril |
RT level testability analysis to reduce test application time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 104-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction |
55 | Harry Hengster, Rolf Drechsler, Bernd Becker 0001 |
On the application of local circuit transformations with special emphasis on path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 387-392, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
local circuit transformations, path delay fault testability, SALT, logic testing, delays, integrated circuit testing, automatic testing |
55 | Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja |
Incorporating testability considerations in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 43-55, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability |
54 | Franco Fummi, Donatella Sciuto, M. Serro |
Synthesis for testability of large complexity controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 180-185, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates |
53 | Sandhya Seshadri, Michael S. Hsiao |
Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 131-145, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
behavioral level, value range, SSA representation, design for testability |
51 | Irith Pomeranz, Sudhakar M. Reddy |
Synthesis for Broadside Testability of Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 221-226, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
broadside tests, standard scan, transition faults, test synthesis, full-scan circuits |
51 | Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina |
Testability Estimation Based on Controllability and Observability Parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 504-514, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang |
Design-for-testability and fault-tolerant techniques for FFT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 732-741, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Dong Xiang, Shan Gu, Hideo Fujiwara |
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 300-305, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
51 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression-based register-transfer level testability analysis and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 824-832, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
51 | A. N. Trahtman |
Piecewise and Local Threshold Testability of DFA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCT ![In: Fundamentals of Computation Theory, 13th International Symposium, FCT 2001, Riga, Latvia, August 22-24, 2001, Proceedings, pp. 347-358, 2001, Springer, 3-540-42487-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
locally threshold testable, piecewise testable, locally testable, syntactic semigroup, algorithm, automaton, transition graph |
51 | Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang |
TAIR: testability analysis by implication reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 152-160, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
51 | Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz |
LOT: Logic Optimization with Testability. New transformations for logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5), pp. 386-399, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
51 | Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 201-212, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
controller resynthesis, test synthesis, high-level testing |
51 | Hingsam S. Fung, Sanford Hirschhorn, R. Kulkarni |
Design for testability in a silicon compilation environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 190-196, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
50 | Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara |
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 415-422, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
design for testability, system-on-a-chip, test scheduling, test access mechanism, consecutive testability |
50 | Frank F. Hsu, Janak H. Patel |
Design for Testability Using State Distances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 93-100, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
state distance, finite-state-machine, design-for-testability, synthesis-for-testability |
50 | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
Testability Insertion in Behavioral Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996., pp. 139-144, 1996, ACM / IEEE Computer Society, 0-8186-7563-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description |
50 | Yu Fang, Alexander Albicki |
Efficient testability enhancement for combinational circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 168-179, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty |
50 | Chunduri Rama Mohan, Partha Pratim Chakrabarti |
Combined optimization of area and testability during state assignment of PLA-based FSM's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 408-413, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization |
50 | Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar |
Testability-oriented channel routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 208-213, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield |
50 | Fabrizio Lombardi, Donatella Sciuto |
Constant testability of combinational cellular tree structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(2), pp. 139-148, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Constant testability, testing, design for testability, finite automata, tree structures |
47 | Phil McMinn |
Search-based failure discovery using testability transformations to generate pseudo-oracles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2009, Proceedings, Montreal, Québec, Canada, July 8-12, 2009, pp. 1689-1696, 2009, ACM, 978-1-60558-325-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
non-testable program, pseudo-oracle, search-based software testing, testability transformation, program transformation, oracle |
47 | Misko Hevery |
Testability explorer: using byte-code analysis to engineer lasting social changes in an organization's software development process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA Companion ![In: Companion to the 23rd Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2008, October 19-13, 2007, Nashville, TN, USA, pp. 747-748, 2008, ACM, 978-1-60558-220-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
byte-code analysis, refactoring, unit testing, testability, social engineering |
47 | Michel Jaring, René L. Krikhaar, Jan Bosch |
Modeling Variability and Testability Interaction in Software Product Line Engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCBSS ![In: Seventh International Conference on Composition-Based Software Systems (ICCBSS 2008), February, 25-29, 2008, Madrid, Spain, Proceedings, pp. 120-129, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
software product line, variability, testability |
47 | Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen |
A Statistic-Based Approach to Testability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 267-270, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fault detection probability, controllability, observability, Testability analysis |
47 | Lian Yu, Lifeng Xu, Guanzhu Wang, Chang Yan Chi, Wenping Xiao, Hui Su |
Testability and Test Framework for Collaborative Real-Time Editing Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QSIC ![In: Seventh International Conference on Quality Software (QSIC 2007), 11-12 October 2007, Portland, Oregon, USA, pp. 322-327, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
timeline diagram, grey-box testing, visualization, collaboration, testability, test framework |
47 | Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto |
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(2), pp. 200-215, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Testing of embedded systems, VHDL, ATPG, fault modeling, testability analysis |
47 | Zuhoor A. Al-Khanjari, Martin R. Woodward, Haider Ali Ramadhan |
Critical Analysis of the PIE Testability Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 10(4), pp. 331-354, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
PIE technique, mutant schemata, testability, sensitivity, infection |
47 | Nguyen Thanh Binh 0002, Michel Delaunay, Chantal Robach |
Testability Analysis for Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 18th International Conference on Software Maintenance (ICSM 2002), Maintaining Distributed Heterogeneous Systems, 3-6 October 2002, Montreal, Quebec, Canada, pp. 422-429, 2002, IEEE Computer Society, 0-7695-1819-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Data-flow Systems, Software Metrics, Testability Analysis, Testing Criteria |
47 | Harry Hengster, Bernd Becker 0001 |
Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 268-275, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits |
47 | Kamel Karoui, Abderrazak Ghedamsi, Rachida Dssouli |
A Study of Some Influencing Factors in Testability and Diagnostics Based on FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the Fourth IEEE Symposium on Computers and Communications (ISCC 1999), 6-8 July 1999, Sharm El Sheikh, Red Sea, Egypt, pp. 109-115, 1999, IEEE Computer Society, 0-7695-0250-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Design, Controllability, Abstraction, Fuzziness, Testability, Diagnostics, Distinguishability |
47 | Kowen Lai, Christos A. Papachristou, Mikhail Baklashov |
BIST testability enhancement using high level test synthesis for behavioral and structural designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 338-342, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST testability, behavioral designs, industrial benchmark, controllability, built-in self test, observability, DFT, transparency, fidelity, structural designs, high level test synthesis |
47 | Marc Perbost, Ludovic Le Lan, Christian Landrault |
Automatic Testability Analysis of Boards and MCMs at Chip Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 36-41, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
DFT, testability analysis, MCM |
47 | Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz |
On minimizing the number of test points needed to achieve complete robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 288-295, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion |
47 | Johannes Steensma, Werner Geurts, Francky Catthoor, Hugo De Man |
Testability analysis in high level data path synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 43-56, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Data path testing, high level synthesis, test pattern generation, testability analysis |
46 | Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki |
A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 263-268, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path |
46 | Srivaths Ravi 0001, Niraj K. Jha |
Test synthesis of systems-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10), pp. 1211-1217, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Frank F. Hsu, Janak H. Patel |
High-Level Controllability and Observability Analysis for Test Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 93-103, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
controllability, observability, high-level test synthesis, behavioral modification |
46 | Christos A. Papachristou, Mikhail Baklashov, Kowen Lai |
High-Level Test Synthesis for Behavioral and Structural Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 167-188, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
built-in self test, DFT, test synthesis |
44 | Dong Xiang, Janak H. Patel |
Partial Scan Design Based on Circuit State Information and Functional Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(3), pp. 276-287, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Valid state, invalid state, testability improvement potential, conflict, testability measure, partial scan design |
44 | Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki |
Cost/Quality Trade-off in Synthesis for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(2), pp. 109-119, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
DFT reuse, BIST, synthesis for testability, testability analysis |
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