Search results for "self-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, George Xenoulis	Software-Based Self-Testing of Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor self-testing, Embedded processors, software-based self-testing, low-cost testing
20	Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus	Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip.	IOLTS	2003	DBLP DOI BibTeX RDF
20	Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita	Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
20	Benoit Provost, Edgar Sánchez-Sinencio, Anna Maria Brosa	A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	NGCC amplifier, BIST, Fault-coverage, Analog testing, Time-domain
20	Richard Illman, Stephen Clarke	Built-In Self-Test of the Macrolan Chip.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
20	Sadeka Ali, Martin Margala	A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.	ITC	2003	DBLP DOI BibTeX RDF	built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair
20	Dariusz Badura, Andrzej Hlawiczka	Low Cost Bist for Edac Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	CBIST, EDAC, error aliasing, fault coverage, self-test
20	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
19	Shantanu Dutt, Vinay Verma, Vishal Suthar	Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang	A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
19	Kazuko Kambe, Michiko Inoue, Hideo Fujiwara	Efficient Template Generation for Instruction-Based Self-Test of Processor Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
19	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell	An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.	VTS	2004	DBLP DOI BibTeX RDF
19	Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton	Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory.	IOLTW	2001	DBLP DOI BibTeX RDF
19	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self-test for DSP cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
19	Eleanor Wu, Paul W. Rutkowski	PEST: a tool for implementing pseudo-exhaustive self test.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
19	Ioannis Voyiatzis	Embedding test patterns into Low-Power BIST sequences.	IOLTS	2007	DBLP DOI BibTeX RDF	Test set embedding, Gray sequences, Low power sequences, Built-In Self Test
19	Scott Davidson 0001	BIST the hard way.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	N-detection, scan BIST, built-in self-test, logic, IC, mixed-signal BIST
19	Li Chen, Sujit Dey	Software-based diagnosis for processors.	DAC	2002	DBLP DOI BibTeX RDF	microprocessor, self-test, instruction, diagnostics
19	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou	Integrated test of interacting controllers and datapaths.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	built-in self-test, register transfer level, synthesis-for-testability
19	Lijian Li, Yinghua Min	An efficient BIST design using LFSR-ROM architecture.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	read-only storage, BIST design, LFSR-ROM architecture, built-in self test, logic design, automatic test pattern generation, test pattern generation, integrated circuit design, shift registers, hardware overhead, ROM, integrated circuit economics
19	Alvernon Walker, Parag K. Lala	A Transition Based BIST Approach for Passive Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Built-in Self Test, Analog Test, Analog BIST, Mixed-Signal BIST
19	Joel A. Jorgenson, Russell J. Wagner	Design-For-Test in a Multiple Substrate Multichip Module.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	Multichip Module (MCM) Test, Known-Good Die (KGD), Ball Grid Array (BGA), Built-In-Self-Test (BIST), boundary-scan
19	Albrecht P. Stroele	BIST Pattern Generators Using Addition and Subtraction Operations.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	built-in self-test, adder, accumulator, pattern generator, subtracter
19	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	On testable multipliers for fixed-width data path architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Fixed-Width Architectures, Built-in Self -Test, High-level Synthesis, Design for Testability
19	Geetani Edirisooriya, John P. Robinson	Cyclic code weight spectra and BIST aliasing.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	compaction aliasing probability, linear code spectra, multiple input signature analysis, Built-in self-test
19	Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar	Hybrid BIST Optimization Using Reseeding and Test Set Compaction.	DSD	2007	DBLP DOI BibTeX RDF
19	Mohammad Tehranipoor, Reza M. Rad	Test and recovery for fine-grained nanoscale architectures.	FPGA	2006	DBLP DOI BibTeX RDF
19	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.	IOLTW	2000	DBLP DOI BibTeX RDF	BIST, Random Testing, Delay Testing, Bridging Faults
19	Albrecht P. Stroele, Hans-Joachim Wunderlich	Hardware-optimal test register insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
19	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.	DAC	1998	DBLP DOI BibTeX RDF
19	Vishnupriya Shivakumar, Chinnaiyan Senthilpari, Zubaida Binti Yusoff	A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture.	IEEE Access	2021	DBLP DOI BibTeX RDF
19	Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin	Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction.	IET Comput. Digit. Tech.	2010	DBLP DOI BibTeX RDF
19	Hisayoshi Hanai, Shinji Yamada, Hisaya Mori, Eisaku Yamashita, Teruhiko Funakura	Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
19	Dariusz Badura	Efficiency of Self-Test Path as a Test Pattern Generator and Test Response Compactor.	Fehlertolerierende Rechensysteme	1989	DBLP DOI BibTeX RDF
19	Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis	Software-Based Self-Test for Pipelined Processors: A Case Study.	DFT	2005	DBLP DOI BibTeX RDF
19	Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus	A Hierarchical Self Test Scheme for SoCs.	IOLTS	2004	DBLP DOI BibTeX RDF
19	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	LI-BIST, crosstalk test, BIST, SoC test, low-power test
19	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	VTS	2002	DBLP DOI BibTeX RDF
19	Laurent Bréhélin, Olivier Gascuel, Gilles Caraux	Hidden Markov Models with Patterns to Learn Boolean Vector Sequences and Application to the Built-In Self-Test for Integrated Circuits.	IEEE Trans. Pattern Anal. Mach. Intell.	2001	DBLP DOI BibTeX RDF
18	Daniel Mange, André Stauffer, Gianluca Tempesti	Embryonics: A Macroscopic View of the Cellular Architecture.	ICES	1998	DBLP DOI BibTeX RDF
18	David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester	Vicis: a reliable network for unreliable silicon.	DAC	2009	DBLP DOI BibTeX RDF	hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy
18	Jack R. Smith, Tian Xia, Charles E. Stroud	An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	stuck-at faults, bridging faults, delay faults
18	Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.	ITC	2003	DBLP DOI BibTeX RDF
18	Jun Zhou 0009, Hans-Joachim Wunderlich	Software-based self-test of processors under power constraints.	DATE	2006	DBLP DOI BibTeX RDF	test program generation, low power test, processor test
18	Dayu Yang, Foster F. Dai, Charles E. Stroud	Built-in self-test for automatic analog frequency response measurement.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen	On A Software-Based Self-Test Methodology and Its Application.	VTS	2005	DBLP DOI BibTeX RDF
18	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment.	VTS	2001	DBLP DOI BibTeX RDF
18	Khoan Truong	A Simple Built-In Self Test For Dual Ported SRAMs.	MTDT	2000	DBLP DOI BibTeX RDF
18	Keiho Akiyama, Kewal K. Saluja	A method of reducing aliasing in a built-in self-test environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	Prawat Nagvajara, Mark G. Karpovsky, Lev B. Levitin	Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
18	Miloslaw Chodacki	Genetic algorithm as self-test path and circular self-test path design method.	Vietnam. J. Comput. Sci.	2018	DBLP DOI BibTeX RDF
18	Miloslaw Chodacki	Genetic Algorithm for Self-Test Path and Circular Self-Test Path Design.	ACIIDS (2)	2017	DBLP DOI BibTeX RDF
18	Hongzhi Li	A BIST (Built-In Self-Test) strategy for mixed-signal integrated circuits (BIST (Built-in Self-Test) Strategie für integrierte Mixed-Signal Schaltungen) (PDF / PS)		2004	RDF
17	Jee-Youl Ryu, Bruce C. Kim	Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	output DC voltage, built-in self-test, low noise amplifier, RFIC
17	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, Built-In Self-Test, delay faults
17	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian	An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	datapath test, shifter, Built-in self-test, accumulator, arithmetic-logic unit, processor test
17	A. Schubert, Walter Anheier	On Random Pattern Testability of Cryptographic VLSI Cores.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	testing of cores, test-ready intellectual property, built-in self-test, pseudorandom testing
17	O. A. Petlin, Stephen B. Furber	Built-In Self-Testing of Micropipelines.	ASYNC	1997	DBLP DOI BibTeX RDF	Built-in self-test, Design for test, Asynchronous design, Micropipelines
17	Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker 0001	On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.	VTS	1997	DBLP DOI BibTeX RDF	input probability, weighted random pattern generation (WRPG), genetic algorithm, Build in self test (BIST)
17	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
17	Geetani Edirisooriya, John P. Robinson	Aliasing properties of circular MISRs.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	multiple input signature analysis, test data compaction, built-in self-test, Aliasing probability
17	Yervant Zorian, Vinod K. Agarwal	Optimizing error masking in BIST by output data modification.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	error masking, improving fault coverage, output data compaction, Built-in self-test
17	Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur	Evaluation of Analog/RF Test Measurements at the Design Stage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
17	Jing Li 0073, Aditya Bansal, Swaroop Ghosh, Kaushik Roy 0001	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
17	Wei Wang, Yu Hu 0001, Yinhe Han 0001, Xiaowei Li 0001, You-Sheng Zhang	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	don’t care bits, minimum leakage vector, leakage power, leakage current
17	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudofunctional testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Livier Lizarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur	Study of a BIST Technique for CMOS Active Pixel Sensors.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
17	Peter Muhmenthaler	New on-Chip DFT and ATE Features for Efficient Embedded Memory Test.	MTDT	2006	DBLP DOI BibTeX RDF
17	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving test effectiveness of scan-based BIST by scan chain partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
17	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
17	Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus	A Hybrid BIST Architecture and Its Optimization for SoC Testing.	ISQED	2002	DBLP DOI BibTeX RDF
17	Shivakumar Swaminathan, Krishnendu Chakrabarty	On Using Twisted-Ring Counters for Test Set Embedding in BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST
17	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	Charles E. Stroud, Ahmed E. Barbour	Testability and test generation for majority voting fault-tolerant circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults
17	Mohammad A. Naal, Emmanuel Simeu, Salvador Mir	On-Line Testable Decimation Filter Design for AMS Systems.	IOLTS	2003	DBLP DOI BibTeX RDF	non-concurrent, semi-concurrent, SigmaDelta, decimation filters, analogue BIST, on-line testing
17	Gerd Krüger 0001	Automatic generation of self-test programs - a new feature of the MIMOLA design system.	DAC	1986	DBLP DOI BibTeX RDF
16	Ramesh Karri, Nilanjan Mukherjee	Versatile BIST: an integrated approach to on-line/off-line BIST.	ITC	1998	DBLP DOI BibTeX RDF
16	Xiaowei Li 0001, Guihai Yan, Cheng Liu 0008	Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach		2023	DOI RDF
16	Xiaowei Li 0001, Guihai Yan, Jing Ye 0001, Ying Wang 0001	Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach.	Sci. China Inf. Sci.	2018	DBLP DOI BibTeX RDF
16	Timothy J. Dysart, Peter M. Kogge	Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder.	DFT	2007	DBLP DOI BibTeX RDF
16	Vishal Suthar, Shantanu Dutt	High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
16	Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni	A Built-In Self-Test Scheme for Differential Ring Oscillators.	ISQED	2005	DBLP DOI BibTeX RDF
16	Dilip K. Bhavsar	A Built-in Self-Test Method for Write-only Content Addressable Memories.	VTS	2005	DBLP DOI BibTeX RDF
16	Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda	Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores.	MTV	2004	DBLP DOI BibTeX RDF
16	Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris	Built-In Self-Test for System-on-Chip: A Case Study.	ITC	2004	DBLP DOI BibTeX RDF
16	Andreas Lechner, J. Ferguson, Andrew Richardson 0001, B. Hermes	A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit .	DATE	1999	DBLP DOI BibTeX RDF
16	Abhijit Chatterjee, Naveena Nagi	Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial.	VLSI Design	1997	DBLP DOI BibTeX RDF
16	Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. Michael Miller, Howard C. Card	Cellular automata-based pseudorandom number generators for built-in self-test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
16	Ronald Stevens, Brittany Parsons, Tariq M. King	A self-testing autonomic container.	ACM Southeast Regional Conference	2007	DBLP DOI BibTeX RDF	testing, validation, autonomic computing
16	Shalini Ghosh, Eric W. MacDonald, Sugato Basu, Nur A. Touba	Low-power weighted pseudo-random BIST using special scan cells.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	weighted pseudo-random testing, low power, built-in self-test
16	Stefan Gerstendörfer, Hans-Joachim Wunderlich	Minimized Power Consumption for Scan-Based BIST.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	build-in self-test (BIST), power consumption
16	Jayabrata Ghosh-Dastidar, Nur A. Touba	A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains.	VTS	2000	DBLP DOI BibTeX RDF	built-in self-test Scan Chains, Design-for-Diagnosis, Multi-Input Signature Register, Design-for-Testability, LFSR, Integrated Circuits, Integrated Circuits, Digital Testing, Design-for-Debug
16	David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi	Testing of programmable logic devices (PLD) with faulty resources.	DFT	1997	DBLP DOI BibTeX RDF	faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
16	Dipanwita Roy Chowdhury, Indranil Sengupta 0001, Parimal Pal Chaudhuri	A class of two-dimensional cellular automata and their applications in random pattern testing.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	cellular automata (CA), pseudo-random patterns, 2-D CA, Built-in self-test
16	Reza M. Rad, Mohammad Tehranipoor	SCT: A novel approach for testing and configuring nanoscale devices.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Configuration and testing, reconfigurable nanoscale devices, fault tolerance, crossbar, nanowire
16	Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan	Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.	VLSI Design	2008	DBLP DOI BibTeX RDF
16	Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao	Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF