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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5912 occurrences of 2755 keywords
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Results
Found 14022 publication records. Showing 14022 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
12 | Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen |
Identification of robust untestable path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 229-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification |
12 | Sandeep Pagey |
Fast functional testing of delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 375-381, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates |
12 | Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell |
Functional test generation for path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 339-345, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults |
12 | Irith Pomeranz, Sudhakar M. Reddy |
Static compaction for two-pattern test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 222-228, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults |
12 | Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu |
Generation of tenacious tests for small gate delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 332-338, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage |
12 | Jacob Savir |
Generator choices for delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 214-221, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test |
12 | Hiroaki Ueda, Kozo Kinoshita |
Low power design and its testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 361-366, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability |
12 | Sandeep Pagey, Ajay Khoche, Erik Brunvand |
DFT for fast testing of self-timed control circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 382-386, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fast testing, self-timed control circuits, execution paths, simultaneous testing, OCCAM based circuit compiler, OCCAM program, self-timed macro-modules, modified modules, macromodules, fault diagnosis, logic testing, delays, design for testability, DFT, logic CAD, asynchronous circuits, translation, program compilers, automatic test software |
12 | Soumitra Bose, Vishwani D. Agrawal |
Sequential logic path delay test generation by symbolic analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 353-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions |
12 | Youngmin Hur, Stephen A. Szygenda |
Special purpose array processor for digital logic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 28st Annual Simulation Symposium (SS '95), April 25-28, 1995, Santa Barbara, California, USA, pp. 297-302, 1995, IEEE Computer Society, 0-8186-7091-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost |
12 | Belle W. Y. Wei, He Du, Honglu Chen |
A complex-number multiplier using radix-4 digits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 84-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme |
12 | Clyde F. Martin, Lawrence Schovanec |
Fatigue Effects in Muscular Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CBMS ![In: Eighth Annual IEEE Symposium on Computer-Based Medical Systems (CBMS'95), June 9-10, 1995, Lubbock, Texas, USA, pp. 188-195, 1995, IEEE Computer Society, 0-8186-7117-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
biocontrol, physiological models, fatigue effects, muscular control model, monosynaptic reflex, muscle dynamics, neural spindle receptors, 4-element viscoelastic models, afferent spindle output, delay effects, stability, stability, delays, feedback, system performance, numerical simulations, biomechanics, feedback loop, muscle, neurophysiology, viscoelasticity |
12 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 687-694, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation |
12 | M. Ryu, Michitaka Kameyama |
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 20-27, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
highly parallel multiple-valued linear digital system, k-ary operations, extended representation matrices, minimum critical path delay, unary operations, sparse representation matrices, output digit, decomposed unary operations, delays, multivalued logic circuits, sparseness, superposition, code assignment, signal representation |
12 | Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng |
Simple tree-construction heuristics for the fanout problem . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 671-679, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
tree-construction heuristics, fanout problem, fanout delay, buffer fanout trees, technology mapped network, gate-transformation, LT-tree construction technique, delays, combinational circuits, trees (mathematics), critical paths, logical functions |
12 | Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang |
A self-timed redundant-binary number to binary number converter for digital arithmetic processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 386-391, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems |
12 | Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito |
A CMOS gate array with dynamic-termination GTL I/O circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 25-29, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays |
12 | Bret Stott, Dave Johnson 0003, Venkatesh Akella |
Asynchronous 2-D discrete cosine transform core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 380-385, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron |
12 | R. Gopalakrishnan, Guru M. Parulkar |
RMDP-a real-time CPU scheduling algorithm to provide QoS guarantees for protocol processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 1st IEEE Real-Time Technology and Applications Symposium, Chicago, Illinois, USA, May 15-17, 1995, pp. 56-57, 1995, IEEE Computer Society, 0-8186-6980-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
RMDP real-time CPU scheduling algorithm, processing guarantees, reduced contest switch operations, bandwidth guarantees, protocol session, NetBSD operating system, simulation, simulation, scheduling, real-time systems, protocols, delays, multimedia applications, processor scheduling, operating systems (computers), multimedia computing, QoS guarantees, delay guarantees, schedulability test, protocol processing |
12 | Hans Lindkvist, Per Andersson |
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 121-130, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic |
12 | Priyadarsan Patra, Donald S. Fussell |
Power-efficient delay-insensitive codes for data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 316-323, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits |
12 | B. Bayerdorffer |
Broadcast Time Warp. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 602-611, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Broadcast Time Warp, correctness constraint, simulation-time order., global virtual time, computational event scheduling, inefficiency, transitivity delay, incremental rollback, virtual-time synchronization protocol, synchronization semantics, scheduling, protocols, distributed algorithms, distributed computations, broadcasting, delays, synchronisation, distributed simulation, partial order, total order, causal order, time warp simulation |
12 | Enrico Macii, Massimo Poncino |
Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 60-65, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation |
12 | Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha |
Improving self-timed pipeline ring performance through the addition of buffer loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 218-223, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
buffer circuits, self-timed pipeline ring performance, buffer loops, communication scheme, communication delay reduction, data communication delay, pace handshaking overhead, initial system configuration, performance evaluation, delays, timing, logic design, asynchronous circuits, pipeline processing |
12 | Uwe Hinsberger, Reiner Kolla |
Optimal technology mapping for single output cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 14-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table |
12 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
Fast algorithm for performance-oriented Steiner routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 198-203, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques |
12 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
12 | Nestoras Tzartzanis, William C. Athas |
Design and analysis of a low-power energy-recovery adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 66-69, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation |
12 | Stanley Habib, Quan Xu |
Technology mapping algorithms for sequential circuits using look-up table based FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 164-167, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table |
12 | Harry Hengster, Rolf Drechsler, Bernd Becker 0001 |
On the application of local circuit transformations with special emphasis on path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 387-392, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
local circuit transformations, path delay fault testability, SALT, logic testing, delays, integrated circuit testing, automatic testing |
12 | Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |
Diagnostic of path and gate delay faults in non-scan sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 380-386, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults |
12 | O. A. Petlin, Stephen B. Furber |
Scan testing of micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines |
12 | Wuudiann Ke, Premachandran R. Menon |
Multifault testability of delay-testable circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 400-409, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits |
12 | Kwang-Ting Cheng |
Partial scan designs without using a separate scan clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 277-282, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock |
12 | Angela Krstic, Kwang-Ting Cheng |
Generation of high quality tests for functional sensitizable paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 374-379, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high quality tests, functional sensitizable paths, long paths, untestable paths, faulty conditions, test derivation, logic testing, delays, timing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, delay testing, test vectors, timing information |
12 | Roberto Baldoni, Achour Mostéfaoui, Michel Raynal |
Efficient Causally Ordered Communications for Multimedia Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 4th International Symposium on High Performance Distributed Computing (HPDC '95), Washington, DC, USA, August 2-4, 1995., pp. 140-147, 1995, IEEE Computer Society, 0-8186-7088-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
causally ordered communications, multimedia real-time applications, groupware real-time applications, real-time delivery constraints, one-to-one communications, protocols, protocol, groupware, delays, abstraction, communication network, multimedia systems, collaborative applications, telecommunication networks |
12 | S. C. Prasad, Kaushik Roy 0001 |
Circuit optimization for minimisation of power consumption under delay constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 305-309, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates |
12 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 171-176, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions |
12 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
An efficient automatic test generation system for path delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 161-165, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests |
12 | Srimat T. Chakradhar |
Optimum retiming of large sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 135-140, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation |
12 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
12 | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
Statistical methods for delay fault coverage analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 166-170, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities |
12 | Sven Simon 0001, Ralf Bucher, Josef A. Nossek |
Retiming of synchronous circuits with variable topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 130-134, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits |
12 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Robust testing for stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 42-46, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models |
12 | Bernhard Albert, Anura P. Jayasumana |
Performance analysis of FDDI LANs using numerical methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 20th Conference on Local Computer Networks (LCN'95), Minneapolis, Minnesota, USA, October 16-19, 1995, pp. 379-386, 1995, IEEE Computer Society, 0-8186-7162-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
FDDI LANs, Mathematica code, graphing capabilities, average access delay estimate, advanced token ring based networks, FFOL, FDDI follow on LAN, medium loaded networks, low loaded networks, symmetric multimedia environment, bimodal traffic, short data packets, video packets, estimated average access time, varied offered load, simulators, performance evaluation, performance analysis, graph theory, virtual machines, delays, local area networks, error analysis, numerical analysis, numerical methods, error rate, symbol manipulation, FDDI, network configuration, confidence measure, token networks |
12 | Kang G. Shin, Chao-Ju Hou |
Design and Evaluation of Effective Load Sharing in Distributed Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(7), pp. 704-719, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
minimum-laxity first-served policy, loss-minimizing decisions, buddy set, Bayesian decision analysis, simulation, performance evaluation, real-time systems, resource allocation, delays, multiprocessing systems, decision theory, Bayes methods, distributed real-time systems, probability distributions, load sharing |
12 | Dilip D. Kandlur, Kang G. Shin, Domenico Ferrari |
Real-Time Communication in Multihop Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(10), pp. 1044-1056, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
unpredictable delays, task execution, predictable interprocess communication, point-to-point interconnection networks, maximum delivery time, unidirectional connection, source-destination communication, sensor station, communications subsystem, delivery time guarantees, scheduling, scheduling, performance evaluation, real-time systems, real-time systems, reliability, parallel architectures, fault tolerant computing, message passing, multiprocessor interconnection networks, real-time communication, multihop networks, performance requirements, buffer allocation, real-time channel, message delivery |
12 | Chunming Qiao, Rami G. Melhem |
Time-Division Optical Communications in Multiprocessor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(5), pp. 577-590, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
optical communication structure, multiprocessor arrays, high communication bandwidth, optical waveguides, optical signal transmissions, unidirectional propagation, predictable propagation delays, message pipelining, TDM approaches, communication effectiveness, clock distribution method, potential synchronization problems, optical waveguides, multiprocessing systems, simulation results, optical communication, time-division multiplexing, time division multiplexing, optical information processing |
12 | Vitit Kantabutra |
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(11), pp. 1389-1393, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron |
12 | Ahmed El-Amawy, Morteza Naraghi-Pour, Manju V. Hegde |
Noise Modeling Effects in Redundant Synchronizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1487-1494, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
redundant synchronizers, jitter model, absorbing barrier problem, clock delay, voter delay, aperture alignment, L-input AND, OR functions, majority voter function, general redundant synchronizer, delays, logic design, noise, combinational circuit, synchronisation, stochastic model, masking, combinatorial circuits, metastability, noise model |
12 | Jenn-Yang Tien, Ching-Tien Ho, Wei-Pang Yang |
Broadcasting on Incomplete Hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(11), pp. 1393-1398, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
edge-disjoint spanning trees, delays, hypercube networks, trees (mathematics), broadcasting algorithm, incomplete hypercube, faulty nodes |
12 | Vitit Kantabutra |
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1495-1499, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders |
12 | Jau-Hsiung Huang, Leonard Kleinrock |
Performance Evaluation of Dynamic Sharing of Processors in Two-Stage Parallel Processing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(3), pp. 306-317, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
dynamic sharing of processors, two-stage parallel processingsystems, mean system delay, mean system time, scale-up rule, approximated delay performance, scheduling, performance evaluation, performance evaluation, parallel processing, delays, job scheduling, approximation model |
12 | K. C. Lee |
A Virtual Bus Architecture for Dynamic Parallel Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(2), pp. 121-130, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
virtual bus architecture, dynamic parallel processing, parallel/distributed machine, end-to-end communication bandwidth, communicationpatterns, data collection operations, nonuniformtraffic, open system parallel interface, open system communication backbone, scheduling, interconnection network, delays, multiprocessor interconnection networks, open systems, dynamic load balancing, network interfaces, queuing delay |
12 | Ashok K. Agrawala, Bijendra N. Jain |
Deterministic Model and Transient Analysis of Virtual Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 19(2), pp. 187-197, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
transit delay, tandem of servers, transit time constraints, minimum transit delay, opensystems, delays, congestion control, computer networks, computer networks, throughput, transient analysis, FIFO, virtual circuits, service times, maximum throughput, deterministic model |
12 | Taieb Znati, Brian Field |
A Network Level Channel Abstraction for Multimedia Communication in Real-Time Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 5(4), pp. 590-599, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
network level channel abstraction, network level abstraction, phi -channel, end-to-end communication channel, packet maximum end-to-end delay, on-time reliability, simulation, protocols, delays, distributed databases, multimedia systems, communication protocols, multimedia communication, distributed multimedia systems, real-time networks, performance parameters |
12 | K. Ravindran, Vivek Bansal |
Delay Compensation Protocols for Synchronization of Multimedia Data Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 5(4), pp. 574-589, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
delay compensation protocols, multimedia data streams, broadband ISDNs, protocols, temporal logic, delays, video, database management systems, multimedia systems, synchronisation, graphics, framing, high speed network, text, voice, metropolitan area networks, data segments, temporal synchronization |
12 | Shahram Ghandeharizadeh, Luis Ramos |
Continuous Retrieval of Multimedia Data Using Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 5(4), pp. 658-669, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
continuous retrieval, parallel multimedia information system, information retrieval, parallelism, delays, database management systems, multimedia systems, simulation model, multimedia data, disk drives, processing capability |
12 | Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala |
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(7), pp. 881-886, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
1-out-of-N code, minimum gate delay, NOR array, NOR-NOR PLA, fault tolerant computing, logic testing, delays, logic design, translator, error detection codes, logic arrays, totally self-checking checker |
12 | Benjamin W. Wah |
Population-Based Learning: A Method for Learning from Examples Under Resource Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 4(5), pp. 454-474, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
population based learning, feedback delays, performance-related heuristic methods, knowledge-lean application, performance evaluation, scalability, quality, performance measures, cost, test scheduling, resource constraints, classifier systems, learning by example, learning from examples, limited resources |
12 | Uriel Feige, Prabhakar Raghavan |
Exact Analysis of Hot-Potato Routing (Extended Abstract) ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 33rd Annual Symposium on Foundations of Computer Science, Pittsburgh, Pennsylvania, USA, 24-27 October 1992, pp. 553-562, 1992, IEEE Computer Society, 0-8186-2900-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
random delays, permutation routing problem, hypercube, deterministic algorithm, packet routing, deflection routing, hot-potato routing |
12 | Sergio A. Felperin, Prabhakar Raghavan, Eli Upfal |
A Theory of Wormhole Routing in Parallel Computers (Extended Abstract) ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 33rd Annual Symposium on Foundations of Computer Science, Pittsburgh, Pennsylvania, USA, 24-27 October 1992, pp. 563-572, 1992, IEEE Computer Society, 0-8186-2900-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
multicomputer architecture, mesh connected networks, initial random delays, parallel computers, wormhole routing, simulation results, packet routing, message routing, butterfly |
12 | Frank Thomson Leighton, Eric J. Schwabe |
Efficient Algorithms for Dynamic Allocation of Distributed Memory ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 32nd Annual Symposium on Foundations of Computer Science, San Juan, Puerto Rico, 1-4 October 1991, pp. 470-479, 1991, IEEE Computer Society, 0-8186-2445-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
local memory resources, online allocation algorithm, near-optimal fashion, service delays, algorithms, parallel system, distributed memory, insertions, deletions, dynamic allocation |
12 | John P. Fishburn |
Clock Skew Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(7), pp. 945-951, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
synchronous digital system, minimum safety margin, performance, linear programs, optimisation, CMOS, circuit analysis computing, flip-flops, circuit simulation, CMOS integrated circuits, path delays, clock signal |
12 | Steven D. Kugelmass, Kenneth Steiglitz |
An Upper Bound on Expected Clock Skew in Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(12), pp. 1475-1477, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
expected clock skew, tree distribution systems, synchronously clocked processing elements, buffer stage, VLSI constraints, H-tree, multiprocessor interconnection networks, statistical model, upper bound, synchronous systems, propagation delays |
12 | Sivarama P. Dandamudi, Derek L. Eager |
Hierarchical Interconnection Networks for Multicomputer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(6), pp. 786-797, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
hierarchical interconnection networks, cost-benefit ratios, performance enhancement schemes, performance evaluation, performance analysis, static analysis, multiprocessor interconnection networks, queueing theory, routing algorithms, queueing analysis, multicomputer systems, queueing delays |
12 | Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg |
Latch-to-Latch Timing Rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(6), pp. 798-808, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
latch-to-latch timing rules, consecutive latch pairs, multiple skew levels, data propagation delays, multiple clock pulse widths, clock phases, logic design, synchronous systems, combinational logic, propagation delay |
12 | Peter Kornerup, David W. Matula |
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1106-1115, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
tree pipeline, Gosper, redundant binary bit-pipelined rational arithmetic, redundant binary representation, rational operands, partial quotient arithmetic algorithm, online arithmetic unit, signed bit level, binary radix, binary rational representation, online delays, simulation, parallel computation, redundancy, interconnection, product, digital arithmetic, number theory, difference, quotient, sum |
12 | Thomas E. Anderson |
The Performance of Spin Lock Alternatives for Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(1), pp. 6-16, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
software queueing, CSMA network protocols, Ethernet backoff, Symmetry Model B, spinlock alternatives, shared-money multiprocessors, atomic instructions, softwarespin-waiting algorithms, dynamic arbitration, parallelprocessing, performance evaluation, distributed system, delays, storage management, multistage interconnection network, shared data structures, shared bus multiprocessors |
12 | Bruno Ciciani, Daniel M. Dias, Philip S. Yu |
Analysis of Replication in Distributed Database Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 2(2), pp. 247-261, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
optimal replication, approximate analytical model, semi-optimistic protocols, transaction mix, distributed sites, available MIPS, performance evaluation, performance evaluation, protocols, delays, distributed databases, concurrency control, sensitivity analysis, response time, data replication, communications delay, overhead, distributed database systems, resource contention, concurrency control protocols, data contention |
12 | Gyungho Lee |
A Performance Bound of Multistage Combining Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(10), pp. 1387-1395, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
multistage combining networks, hot-spot traffic, performance evaluation, delays, multiprocessor interconnection networks, performance bound |
12 | Hon Fung Li, R. Jayakumar, Clement Wing Hong Lam |
Restructuring for Fault-Tolerant Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(2), pp. 307-311, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
fault-tolerant systolic arrays, faulty cells, data-flow paths, computational sites, programmable delays, fault tolerant computing, cellular arrays, restructuring, processing elements, data skewing |
12 | Tao Jiang 0001 |
The Synchronization of Nonuniform Networks of Finite Automata (Extended Abstract) ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 30th Annual Symposium on Foundations of Computer Science, Research Triangle Park, North Carolina, USA, 30 October - 1 November 1989, pp. 376-381, 1989, IEEE Computer Society, 0-8186-1982-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
nonuniform networks, generalized firing squad synchronization problem, GFSSP, synchronization, finite automata, transmission delays |
12 | Mark G. Karpovsky |
Multilevel Logical Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(2), pp. 215-226, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
time and space complexity of gate arrays, AND-OR implementations of systems of Boolean functions, gate counts, multilevel logical networks, delays, gate arrays |
12 | Stephen H. Unger, Chung-Jen Tan |
Clocking Schemes for High-Speed Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(10), pp. 880-895, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits |
12 | Peter G. Harrison |
An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(1), pp. 54-61, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
performance evaluation, queueing models, error bounds, time delays, incremental algorithm, computer systems modeling, Approximate analysis |
12 | Guoliang Wei, Gang Feng 0001, Zidong Wang |
Robust H∞ Control for Discrete-Time Fuzzy Systems With Infinite-Distributed Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Fuzzy Syst. ![In: IEEE Trans. Fuzzy Syst. 17(1), pp. 224-232, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Yashun Zhang, Shengyuan Xu, Baoyong Zhang |
Robust Output Feedback Stabilization for Uncertain Discrete-Time Fuzzy Markovian Jump Systems With Time-Varying Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Fuzzy Syst. ![In: IEEE Trans. Fuzzy Syst. 17(2), pp. 411-420, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Changchun Hua, Peter X. Liu |
Delay-dependent stability analysis of teleoperation systems with unsymmetric time-varying delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2009 IEEE International Conference on Robotics and Automation, ICRA 2009, Kobe, Japan, May 12-17, 2009, pp. 1146-1151, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Johnatan E. Pecero, Denis Trystram, Albert Y. Zomaya |
A New Genetic Algorithm for Scheduling for Large Communication Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 241-252, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Fengjian Yang, Chaolong Zhang 0003, Dongqing Wu, Jianfu Yang, Yanshan Zeng, Lishi Liang, Qun Hong |
Global Stability of Neural Networks with Delays and Impulses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 455-462, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
neural network, stability, delay, impulse |
12 | Quanxin Cheng, Haibo Bao, Jinde Cao |
A Delay Fractioning Approach to Global Synchronization of Complex Networks with Distributed Delays and Stochastic Disturbances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 492-502, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Global asymptotic synchronization, Delay fractioning, Stochastic disturbance, Distributed delay, Lyapunov functional |
12 | Guozheng Wang, Qianhong Zhang, Zhenguo Luo |
Global Exponential Stability of FCNNs with Bounded Uncertain Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 383-394, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Fuzzy cellular neural networks, Homeomorphism theory, Lyapunov functional, Global exponential stability, Equilibrium point |
12 | Rui Zhang, Zhanshan Wang, Jian Feng 0001, Yuanwei Jing |
Delay-Dependent Exponential Stability of Discrete-Time BAM Neural Networks with Time Varying Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 440-449, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
BAM neural network, Discrete lyapunov functional, Linear matrix inequality (LMI), Global exponential stability, Discrete-time system |
12 | Tingyan Xing, Muyao Shi, Wenjie Jiang, Nan Zhang, Tuo Wang |
Exponential Stability of Impulsive Hopfield Neural Networks with Time Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 503-511, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Meiqin Liu, Senlin Zhang, Meikang Qiu |
Hinfinity Synchronization of General Discrete-Time Chaotic Neural Networks with Time Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 366-374, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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12 | Gokhan Sahin |
Predictive Scheduling in Rate-Adaptive Multi-user Relay Channels with Reconfiguration Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 29th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2009 Workshops), 22-26 June 2009, Montreal, Québec, Canada, pp. 517-522, 2009, IEEE Computer Society, 978-0-7695-3660-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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12 | Kunal P. Ganeshpure, Sandip Kundu |
An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 233-238, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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12 | Huaguang Zhang, Yingchun Wang, Derong Liu 0001 |
Delay-Dependent Guaranteed Cost Control for Uncertain Stochastic Fuzzy Systems With Multiple Time Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Part B ![In: IEEE Trans. Syst. Man Cybern. Part B 38(1), pp. 126-140, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Chang-Hua Lien, Ker-Wei Yu, Yen-Feng Lin, Yeong-Jay Chung, Long-Yeu Chung |
Global Exponential Stability for Uncertain Delayed Neural Networks of Neutral Type With Mixed Time Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Part B ![In: IEEE Trans. Syst. Man Cybern. Part B 38(3), pp. 709-720, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Daniel E. Quevedo, Eduardo I. Silva, Graham C. Goodwin |
Control over unreliable networks affected by packet erasures and variable transmission delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 26(4), pp. 672-685, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | LinYing Xiang, Zhongxin Liu, Zengqiang Chen 0001, Zhuzhi Yuan |
Pinning weighted complex networks with heterogeneous delays by a small number of feedback controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(5), pp. 511-523, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
complex dynamical network, pinning control, heterogeneous delay, linear matrix inequality (LMI), weighted network |
12 | Gesualdo Scutari, Sergio Barbarossa, Loreto Pescosolido |
Distributed Decision Through Self-Synchronizing Sensor Networks in the Presence of Propagation Delays and Asymmetric Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(4), pp. 1667-1684, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Ha Thai Nguyen, Minh N. Do |
Hybrid Filter Banks With Fractional Delays: Minimax Design and Application to Multichannel Sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(7-2), pp. 3180-3190, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Hongbin Zhang 0002, Chuangyin Dang |
Piecewise H∞ Controller Design of Uncertain Discrete-Time Fuzzy Systems With Time Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Fuzzy Syst. ![In: IEEE Trans. Fuzzy Syst. 16(6), pp. 1649-1655, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Jinde Cao, Fengli Ren |
Exponential Stability of Discrete-Time Genetic Regulatory Networks With Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 19(3), pp. 520-523, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Zhaohui Yuan, Lihong Huang, Dewen Hu, Bingwen Liu |
Convergence of Nonautonomous Cohen-Grossberg-Type Neural Networks With Variable Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 19(1), pp. 140-147, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Xin-Ge Liu, Ralph R. Martin, Min Wu 0002, Mei-Lan Tang |
Global Exponential Stability of Bidirectional Associative Memory Neural Networks With Time Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 19(3), pp. 397-407, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Xinzhi Liu, Qing Wang 0057 |
Impulsive Stabilization of High-Order Hopfield-Type Neural Networks With Time-Varying Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 19(1), pp. 71-79, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Daniel C. Schultz, Ralf Pabst, Bernhard Walke |
Analytical Estimation of Packet Delays in Relay-Based IMT-Advanced Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 67th IEEE Vehicular Technology Conference, VTC Spring 2008, 11-14 May 2008, Singapore, pp. 2411-2415, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
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