Search results for "delays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
12	Sandeep Pagey	Fast functional testing of delay-insensitive circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates
12	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
12	Irith Pomeranz, Sudhakar M. Reddy	Static compaction for two-pattern test sets.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults
12	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
12	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
12	Hiroaki Ueda, Kozo Kinoshita	Low power design and its testability.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
12	Sandeep Pagey, Ajay Khoche, Erik Brunvand	DFT for fast testing of self-timed control circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fast testing, self-timed control circuits, execution paths, simultaneous testing, OCCAM based circuit compiler, OCCAM program, self-timed macro-modules, modified modules, macromodules, fault diagnosis, logic testing, delays, design for testability, DFT, logic CAD, asynchronous circuits, translation, program compilers, automatic test software
12	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
12	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
12	Belle W. Y. Wei, He Du, Honglu Chen	A complex-number multiplier using radix-4 digits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme
12	Clyde F. Martin, Lawrence Schovanec	Fatigue Effects in Muscular Control.	CBMS	1995	DBLP DOI BibTeX RDF	biocontrol, physiological models, fatigue effects, muscular control model, monosynaptic reflex, muscle dynamics, neural spindle receptors, 4-element viscoelastic models, afferent spindle output, delay effects, stability, stability, delays, feedback, system performance, numerical simulations, biomechanics, feedback loop, muscle, neurophysiology, viscoelasticity
12	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
12	M. Ryu, Michitaka Kameyama	Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices.	ISMVL	1995	DBLP DOI BibTeX RDF	highly parallel multiple-valued linear digital system, k-ary operations, extended representation matrices, minimum critical path delay, unary operations, sparse representation matrices, output digit, decomposed unary operations, delays, multivalued logic circuits, sparseness, superposition, code assignment, signal representation
12	Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng	Simple tree-construction heuristics for the fanout problem .	ICCD	1995	DBLP DOI BibTeX RDF	tree-construction heuristics, fanout problem, fanout delay, buffer fanout trees, technology mapped network, gate-transformation, LT-tree construction technique, delays, combinational circuits, trees (mathematics), critical paths, logical functions
12	Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang	A self-timed redundant-binary number to binary number converter for digital arithmetic processors.	ICCD	1995	DBLP DOI BibTeX RDF	convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems
12	Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito	A CMOS gate array with dynamic-termination GTL I/O circuits.	ICCD	1995	DBLP DOI BibTeX RDF	CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays
12	Bret Stott, Dave Johnson 0003, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor.	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
12	R. Gopalakrishnan, Guru M. Parulkar	RMDP-a real-time CPU scheduling algorithm to provide QoS guarantees for protocol processing.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	RMDP real-time CPU scheduling algorithm, processing guarantees, reduced contest switch operations, bandwidth guarantees, protocol session, NetBSD operating system, simulation, simulation, scheduling, real-time systems, protocols, delays, multimedia applications, processor scheduling, operating systems (computers), multimedia computing, QoS guarantees, delay guarantees, schedulability test, protocol processing
12	Hans Lindkvist, Per Andersson	Dynamic CMOS circuit techniques for delay and power reduction in parallel adders .	ARVLSI	1995	DBLP DOI BibTeX RDF	dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic
12	Priyadarsan Patra, Donald S. Fussell	Power-efficient delay-insensitive codes for data transmission.	HICSS (1)	1995	DBLP DOI BibTeX RDF	telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits
12	B. Bayerdorffer	Broadcast Time Warp.	HICSS (2)	1995	DBLP DOI BibTeX RDF	Broadcast Time Warp, correctness constraint, simulation-time order., global virtual time, computational event scheduling, inefficiency, transitivity delay, incremental rollback, virtual-time synchronization protocol, synchronization semantics, scheduling, protocols, distributed algorithms, distributed computations, broadcasting, delays, synchronisation, distributed simulation, partial order, total order, causal order, time warp simulation
12	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
12	Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha	Improving self-timed pipeline ring performance through the addition of buffer loops.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	buffer circuits, self-timed pipeline ring performance, buffer loops, communication scheme, communication delay reduction, data communication delay, pace handshaking overhead, initial system configuration, performance evaluation, delays, timing, logic design, asynchronous circuits, pipeline processing
12	Uwe Hinsberger, Reiner Kolla	Optimal technology mapping for single output cells.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table
12	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Fast algorithm for performance-oriented Steiner routing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques
12	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
12	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
12	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
12	Harry Hengster, Rolf Drechsler, Bernd Becker 0001	On the application of local circuit transformations with special emphasis on path delay fault testability.	VTS	1995	DBLP DOI BibTeX RDF	local circuit transformations, path delay fault testability, SALT, logic testing, delays, integrated circuit testing, automatic testing
12	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	Diagnostic of path and gate delay faults in non-scan sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
12	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
12	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
12	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
12	Angela Krstic, Kwang-Ting Cheng	Generation of high quality tests for functional sensitizable paths.	VTS	1995	DBLP DOI BibTeX RDF	high quality tests, functional sensitizable paths, long paths, untestable paths, faulty conditions, test derivation, logic testing, delays, timing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, delay testing, test vectors, timing information
12	Roberto Baldoni, Achour Mostéfaoui, Michel Raynal	Efficient Causally Ordered Communications for Multimedia Real-Time Applications.	HPDC	1995	DBLP DOI BibTeX RDF	causally ordered communications, multimedia real-time applications, groupware real-time applications, real-time delivery constraints, one-to-one communications, protocols, protocol, groupware, delays, abstraction, communication network, multimedia systems, collaborative applications, telecommunication networks
12	S. C. Prasad, Kaushik Roy 0001	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
12	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
12	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
12	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
12	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
12	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Statistical methods for delay fault coverage analysis.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
12	Sven Simon 0001, Ralf Bucher, Josef A. Nossek	Retiming of synchronous circuits with variable topology.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits
12	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
12	Bernhard Albert, Anura P. Jayasumana	Performance analysis of FDDI LANs using numerical methods.	LCN	1995	DBLP DOI BibTeX RDF	FDDI LANs, Mathematica code, graphing capabilities, average access delay estimate, advanced token ring based networks, FFOL, FDDI follow on LAN, medium loaded networks, low loaded networks, symmetric multimedia environment, bimodal traffic, short data packets, video packets, estimated average access time, varied offered load, simulators, performance evaluation, performance analysis, graph theory, virtual machines, delays, local area networks, error analysis, numerical analysis, numerical methods, error rate, symbol manipulation, FDDI, network configuration, confidence measure, token networks
12	Kang G. Shin, Chao-Ju Hou	Design and Evaluation of Effective Load Sharing in Distributed Real-Time Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	minimum-laxity first-served policy, loss-minimizing decisions, buddy set, Bayesian decision analysis, simulation, performance evaluation, real-time systems, resource allocation, delays, multiprocessing systems, decision theory, Bayes methods, distributed real-time systems, probability distributions, load sharing
12	Dilip D. Kandlur, Kang G. Shin, Domenico Ferrari	Real-Time Communication in Multihop Networks.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	unpredictable delays, task execution, predictable interprocess communication, point-to-point interconnection networks, maximum delivery time, unidirectional connection, source-destination communication, sensor station, communications subsystem, delivery time guarantees, scheduling, scheduling, performance evaluation, real-time systems, real-time systems, reliability, parallel architectures, fault tolerant computing, message passing, multiprocessor interconnection networks, real-time communication, multihop networks, performance requirements, buffer allocation, real-time channel, message delivery
12	Chunming Qiao, Rami G. Melhem	Time-Division Optical Communications in Multiprocessor Arrays.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	optical communication structure, multiprocessor arrays, high communication bandwidth, optical waveguides, optical signal transmissions, unidirectional propagation, predictable propagation delays, message pipelining, TDM approaches, communication effectiveness, clock distribution method, potential synchronization problems, optical waveguides, multiprocessing systems, simulation results, optical communication, time-division multiplexing, time division multiplexing, optical information processing
12	Vitit Kantabutra	Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron
12	Ahmed El-Amawy, Morteza Naraghi-Pour, Manju V. Hegde	Noise Modeling Effects in Redundant Synchronizers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	redundant synchronizers, jitter model, absorbing barrier problem, clock delay, voter delay, aperture alignment, L-input AND, OR functions, majority voter function, general redundant synchronizer, delays, logic design, noise, combinational circuit, synchronisation, stochastic model, masking, combinatorial circuits, metastability, noise model
12	Jenn-Yang Tien, Ching-Tien Ho, Wei-Pang Yang	Broadcasting on Incomplete Hypercubes.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	edge-disjoint spanning trees, delays, hypercube networks, trees (mathematics), broadcasting algorithm, incomplete hypercube, faulty nodes
12	Vitit Kantabutra	A Recursive Carry-Lookahead/Carry-Select Hybrid Adder.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders
12	Jau-Hsiung Huang, Leonard Kleinrock	Performance Evaluation of Dynamic Sharing of Processors in Two-Stage Parallel Processing Systems.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	dynamic sharing of processors, two-stage parallel processingsystems, mean system delay, mean system time, scale-up rule, approximated delay performance, scheduling, performance evaluation, performance evaluation, parallel processing, delays, job scheduling, approximation model
12	K. C. Lee	A Virtual Bus Architecture for Dynamic Parallel Processing.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	virtual bus architecture, dynamic parallel processing, parallel/distributed machine, end-to-end communication bandwidth, communicationpatterns, data collection operations, nonuniformtraffic, open system parallel interface, open system communication backbone, scheduling, interconnection network, delays, multiprocessor interconnection networks, open systems, dynamic load balancing, network interfaces, queuing delay
12	Ashok K. Agrawala, Bijendra N. Jain	Deterministic Model and Transient Analysis of Virtual Circuits.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	transit delay, tandem of servers, transit time constraints, minimum transit delay, opensystems, delays, congestion control, computer networks, computer networks, throughput, transient analysis, FIFO, virtual circuits, service times, maximum throughput, deterministic model
12	Taieb Znati, Brian Field	A Network Level Channel Abstraction for Multimedia Communication in Real-Time Networks.	IEEE Trans. Knowl. Data Eng.	1993	DBLP DOI BibTeX RDF	network level channel abstraction, network level abstraction, phi -channel, end-to-end communication channel, packet maximum end-to-end delay, on-time reliability, simulation, protocols, delays, distributed databases, multimedia systems, communication protocols, multimedia communication, distributed multimedia systems, real-time networks, performance parameters
12	K. Ravindran, Vivek Bansal	Delay Compensation Protocols for Synchronization of Multimedia Data Streams.	IEEE Trans. Knowl. Data Eng.	1993	DBLP DOI BibTeX RDF	delay compensation protocols, multimedia data streams, broadband ISDNs, protocols, temporal logic, delays, video, database management systems, multimedia systems, synchronisation, graphics, framing, high speed network, text, voice, metropolitan area networks, data segments, temporal synchronization
12	Shahram Ghandeharizadeh, Luis Ramos	Continuous Retrieval of Multimedia Data Using Parallelism.	IEEE Trans. Knowl. Data Eng.	1993	DBLP DOI BibTeX RDF	continuous retrieval, parallel multimedia information system, information retrieval, parallelism, delays, database management systems, multimedia systems, simulation model, multimedia data, disk drives, processing capability
12	Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala	A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	1-out-of-N code, minimum gate delay, NOR array, NOR-NOR PLA, fault tolerant computing, logic testing, delays, logic design, translator, error detection codes, logic arrays, totally self-checking checker
12	Benjamin W. Wah	Population-Based Learning: A Method for Learning from Examples Under Resource Constraints.	IEEE Trans. Knowl. Data Eng.	1992	DBLP DOI BibTeX RDF	population based learning, feedback delays, performance-related heuristic methods, knowledge-lean application, performance evaluation, scalability, quality, performance measures, cost, test scheduling, resource constraints, classifier systems, learning by example, learning from examples, limited resources
12	Uriel Feige, Prabhakar Raghavan	Exact Analysis of Hot-Potato Routing (Extended Abstract)	FOCS	1992	DBLP DOI BibTeX RDF	random delays, permutation routing problem, hypercube, deterministic algorithm, packet routing, deflection routing, hot-potato routing
12	Sergio A. Felperin, Prabhakar Raghavan, Eli Upfal	A Theory of Wormhole Routing in Parallel Computers (Extended Abstract)	FOCS	1992	DBLP DOI BibTeX RDF	multicomputer architecture, mesh connected networks, initial random delays, parallel computers, wormhole routing, simulation results, packet routing, message routing, butterfly
12	Frank Thomson Leighton, Eric J. Schwabe	Efficient Algorithms for Dynamic Allocation of Distributed Memory	FOCS	1991	DBLP DOI BibTeX RDF	local memory resources, online allocation algorithm, near-optimal fashion, service delays, algorithms, parallel system, distributed memory, insertions, deletions, dynamic allocation
12	John P. Fishburn	Clock Skew Optimization.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	synchronous digital system, minimum safety margin, performance, linear programs, optimisation, CMOS, circuit analysis computing, flip-flops, circuit simulation, CMOS integrated circuits, path delays, clock signal
12	Steven D. Kugelmass, Kenneth Steiglitz	An Upper Bound on Expected Clock Skew in Synchronous Systems.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	expected clock skew, tree distribution systems, synchronously clocked processing elements, buffer stage, VLSI constraints, H-tree, multiprocessor interconnection networks, statistical model, upper bound, synchronous systems, propagation delays
12	Sivarama P. Dandamudi, Derek L. Eager	Hierarchical Interconnection Networks for Multicomputer Systems.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	hierarchical interconnection networks, cost-benefit ratios, performance enhancement schemes, performance evaluation, performance analysis, static analysis, multiprocessor interconnection networks, queueing theory, routing algorithms, queueing analysis, multicomputer systems, queueing delays
12	Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg	Latch-to-Latch Timing Rules.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	latch-to-latch timing rules, consecutive latch pairs, multiple skew levels, data propagation delays, multiple clock pulse widths, clock phases, logic design, synchronous systems, combinational logic, propagation delay
12	Peter Kornerup, David W. Matula	An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	tree pipeline, Gosper, redundant binary bit-pipelined rational arithmetic, redundant binary representation, rational operands, partial quotient arithmetic algorithm, online arithmetic unit, signed bit level, binary radix, binary rational representation, online delays, simulation, parallel computation, redundancy, interconnection, product, digital arithmetic, number theory, difference, quotient, sum
12	Thomas E. Anderson	The Performance of Spin Lock Alternatives for Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	software queueing, CSMA network protocols, Ethernet backoff, Symmetry Model B, spinlock alternatives, shared-money multiprocessors, atomic instructions, softwarespin-waiting algorithms, dynamic arbitration, parallelprocessing, performance evaluation, distributed system, delays, storage management, multistage interconnection network, shared data structures, shared bus multiprocessors
12	Bruno Ciciani, Daniel M. Dias, Philip S. Yu	Analysis of Replication in Distributed Database Systems.	IEEE Trans. Knowl. Data Eng.	1990	DBLP DOI BibTeX RDF	optimal replication, approximate analytical model, semi-optimistic protocols, transaction mix, distributed sites, available MIPS, performance evaluation, performance evaluation, protocols, delays, distributed databases, concurrency control, sensitivity analysis, response time, data replication, communications delay, overhead, distributed database systems, resource contention, concurrency control protocols, data contention
12	Gyungho Lee	A Performance Bound of Multistage Combining Networks.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	multistage combining networks, hot-spot traffic, performance evaluation, delays, multiprocessor interconnection networks, performance bound
12	Hon Fung Li, R. Jayakumar, Clement Wing Hong Lam	Restructuring for Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, faulty cells, data-flow paths, computational sites, programmable delays, fault tolerant computing, cellular arrays, restructuring, processing elements, data skewing
12	Tao Jiang 0001	The Synchronization of Nonuniform Networks of Finite Automata (Extended Abstract)	FOCS	1989	DBLP DOI BibTeX RDF	nonuniform networks, generalized firing squad synchronization problem, GFSSP, synchronization, finite automata, transmission delays
12	Mark G. Karpovsky	Multilevel Logical Networks.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	time and space complexity of gate arrays, AND-OR implementations of systems of Boolean functions, gate counts, multilevel logical networks, delays, gate arrays
12	Stephen H. Unger, Chung-Jen Tan	Clocking Schemes for High-Speed Digital Systems.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits
12	Peter G. Harrison	An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	performance evaluation, queueing models, error bounds, time delays, incremental algorithm, computer systems modeling, Approximate analysis
12	Guoliang Wei, Gang Feng 0001, Zidong Wang	Robust H∞ Control for Discrete-Time Fuzzy Systems With Infinite-Distributed Delays.	IEEE Trans. Fuzzy Syst.	2009	DBLP DOI BibTeX RDF
12	Yashun Zhang, Shengyuan Xu, Baoyong Zhang	Robust Output Feedback Stabilization for Uncertain Discrete-Time Fuzzy Markovian Jump Systems With Time-Varying Delays.	IEEE Trans. Fuzzy Syst.	2009	DBLP DOI BibTeX RDF
12	Changchun Hua, Peter X. Liu	Delay-dependent stability analysis of teleoperation systems with unsymmetric time-varying delays.	ICRA	2009	DBLP DOI BibTeX RDF
12	Johnatan E. Pecero, Denis Trystram, Albert Y. Zomaya	A New Genetic Algorithm for Scheduling for Large Communication Delays.	Euro-Par	2009	DBLP DOI BibTeX RDF
12	Fengjian Yang, Chaolong Zhang 0003, Dongqing Wu, Jianfu Yang, Yanshan Zeng, Lishi Liang, Qun Hong	Global Stability of Neural Networks with Delays and Impulses.	ISNN (1)	2009	DBLP DOI BibTeX RDF	neural network, stability, delay, impulse
12	Quanxin Cheng, Haibo Bao, Jinde Cao	A Delay Fractioning Approach to Global Synchronization of Complex Networks with Distributed Delays and Stochastic Disturbances.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Global asymptotic synchronization, Delay fractioning, Stochastic disturbance, Distributed delay, Lyapunov functional
12	Guozheng Wang, Qianhong Zhang, Zhenguo Luo	Global Exponential Stability of FCNNs with Bounded Uncertain Delays.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Fuzzy cellular neural networks, Homeomorphism theory, Lyapunov functional, Global exponential stability, Equilibrium point
12	Rui Zhang, Zhanshan Wang, Jian Feng 0001, Yuanwei Jing	Delay-Dependent Exponential Stability of Discrete-Time BAM Neural Networks with Time Varying Delays.	ISNN (1)	2009	DBLP DOI BibTeX RDF	BAM neural network, Discrete lyapunov functional, Linear matrix inequality (LMI), Global exponential stability, Discrete-time system
12	Tingyan Xing, Muyao Shi, Wenjie Jiang, Nan Zhang, Tuo Wang	Exponential Stability of Impulsive Hopfield Neural Networks with Time Delays.	ISNN (1)	2009	DBLP DOI BibTeX RDF
12	Meiqin Liu, Senlin Zhang, Meikang Qiu	Hinfinity Synchronization of General Discrete-Time Chaotic Neural Networks with Time Delays.	ISNN (1)	2009	DBLP DOI BibTeX RDF
12	Gokhan Sahin	Predictive Scheduling in Rate-Adaptive Multi-user Relay Channels with Reconfiguration Delays.	ICDCS Workshops	2009	DBLP DOI BibTeX RDF
12	Kunal P. Ganeshpure, Sandip Kundu	An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Huaguang Zhang, Yingchun Wang, Derong Liu 0001	Delay-Dependent Guaranteed Cost Control for Uncertain Stochastic Fuzzy Systems With Multiple Time Delays.	IEEE Trans. Syst. Man Cybern. Part B	2008	DBLP DOI BibTeX RDF
12	Chang-Hua Lien, Ker-Wei Yu, Yen-Feng Lin, Yeong-Jay Chung, Long-Yeu Chung	Global Exponential Stability for Uncertain Delayed Neural Networks of Neutral Type With Mixed Time Delays.	IEEE Trans. Syst. Man Cybern. Part B	2008	DBLP DOI BibTeX RDF
12	Daniel E. Quevedo, Eduardo I. Silva, Graham C. Goodwin	Control over unreliable networks affected by packet erasures and variable transmission delays.	IEEE J. Sel. Areas Commun.	2008	DBLP DOI BibTeX RDF
12	LinYing Xiang, Zhongxin Liu, Zengqiang Chen 0001, Zhuzhi Yuan	Pinning weighted complex networks with heterogeneous delays by a small number of feedback controllers.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	complex dynamical network, pinning control, heterogeneous delay, linear matrix inequality (LMI), weighted network
12	Gesualdo Scutari, Sergio Barbarossa, Loreto Pescosolido	Distributed Decision Through Self-Synchronizing Sensor Networks in the Presence of Propagation Delays and Asymmetric Channels.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
12	Ha Thai Nguyen, Minh N. Do	Hybrid Filter Banks With Fractional Delays: Minimax Design and Application to Multichannel Sampling.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
12	Hongbin Zhang 0002, Chuangyin Dang	Piecewise H∞ Controller Design of Uncertain Discrete-Time Fuzzy Systems With Time Delays.	IEEE Trans. Fuzzy Syst.	2008	DBLP DOI BibTeX RDF
12	Jinde Cao, Fengli Ren	Exponential Stability of Discrete-Time Genetic Regulatory Networks With Delays.	IEEE Trans. Neural Networks	2008	DBLP DOI BibTeX RDF
12	Zhaohui Yuan, Lihong Huang, Dewen Hu, Bingwen Liu	Convergence of Nonautonomous Cohen-Grossberg-Type Neural Networks With Variable Delays.	IEEE Trans. Neural Networks	2008	DBLP DOI BibTeX RDF
12	Xin-Ge Liu, Ralph R. Martin, Min Wu 0002, Mei-Lan Tang	Global Exponential Stability of Bidirectional Associative Memory Neural Networks With Time Delays.	IEEE Trans. Neural Networks	2008	DBLP DOI BibTeX RDF
12	Xinzhi Liu, Qing Wang 0057	Impulsive Stabilization of High-Order Hopfield-Type Neural Networks With Time-Varying Delays.	IEEE Trans. Neural Networks	2008	DBLP DOI BibTeX RDF
12	Daniel C. Schultz, Ralf Pabst, Bernhard Walke	Analytical Estimation of Packet Delays in Relay-Based IMT-Advanced Networks.	VTC Spring	2008	DBLP DOI BibTeX RDF