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Searching for phrase Clock-gating (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1996-2000 (19) 2001-2002 (15) 2003 (16) 2004 (19) 2005 (20) 2006 (23) 2007 (24) 2008 (24) 2009 (29) 2010 (18) 2011-2012 (27) 2013 (15) 2014-2015 (17) 2016-2018 (18) 2019-2021 (19) 2022-2023 (15) 2024 (1)
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article(80) inproceedings(239)
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ISLPED(22) DAC(15) ISCAS(15) PATMOS(14) ASP-DAC(10) DATE(10) IEEE Trans. Very Large Scale I...(10) IEEE Trans. Comput. Aided Des....(9) VLSI Design(9) ICCD(8) HPCA(6) ICCAD(6) ISQED(6) ISVLSI(6) DSD(5) ISCAS (2)(5) More (+10 of total 119)
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Found 319 publication records. Showing 319 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
132Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed A new paradigm for synthesis and propagation of clock gating conditions. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low-power design, clock gating
120Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF architecture, power, temperature, clock gating
114Eli Arbel, Cindy Eisner, Oleg Rokhlenko Resurrecting infeasible clock-gating functions. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF clustering, low power, approximation, clock gating
113Vishwanadh Tirumalashetty, Hamid Mahmoodi Clock Gating and Negative Edge Triggering for Energy Recovery Clock. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
109Nainesh Agarwal, Nikitas J. Dimopoulos DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
105Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. Search on Bibsonomy HPCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
105Pilar Parra Fernández, Antonio J. Acosta 0001, Manuel Valencia-Barrero Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
105Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu Type-matching clock tree for zero skew clock gating. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF physical design, gated clock, clock network synthesis
104Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou 0001 Improve clock gating through power-optimal enable function selection. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
101Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel Power-Clock Gating in Adiabatic Logic Circuits. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
93Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu Gate planning during placement for gated clock network. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
90Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai A low power VLIW processor generation method by means of extracting non-redundant activation conditions. Search on Bibsonomy CODES+ISSS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low power, ASIP, clock gating, VLIW processor
90Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu Logic synthesis for low power using clock gating and rewiring. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF low power, logic synthesis, clock gating
90Hans M. Jacobson Improved clock-gating through transparent pipelining. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
87Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
85Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii Clock-tree power optimization based on RTL clock-gating. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF clock-tree synthsis, low-power design
85Fei Li 0003, Lei He 0001 Maximum current estimation considering power gating. Search on Bibsonomy ISPD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF low-power design, ATPG, power estimation, power gating
83Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
82Nainesh Agarwal, Nikitas J. Dimopoulos Efficient Automated Clock Gating Using CoDeL. Search on Bibsonomy SAMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
81Chunhong Chen, Changjun Kang, Majid Sarrafzadeh Activity-sensitive clock tree construction for low power. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF low power, clock gating, clock tree, activity pattern
80Nithya Raghavan, Venkatesh Akella, Smita Bakshi Automatic Insertion of Gated Clocks at Register Transfer Level. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
80Ashutosh Chakraborty, David Z. Pan Skew management of NBTI impacted gated clock trees. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF clock skew, clock gating, NBTI
78Xiaotao Chang, Mingming Zhang, Ge Zhang 0007, Zhimin Zhang, Jun Wang Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
78Yan Zhang, Jussi Roivainen, Aarne Mämmelä Clock-Gating in FPGAs: A Novel and Comparative Evaluation. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
72Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang A novel sequential circuit optimization with clock gating logic. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
72Aaron P. Hurst Automatic synthesis of clock gating logic with controlled netlist perturbation. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low power, clock gating, logic optimization, dynamic power
69Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu Activity and register placement aware gated clock network design. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF gated clock tree, low power, placement
68Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri A novel clock distribution and dynamic de-skewing methodology. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
68Li Li, Ken Choi, Seongmo Park, MooKyung Chung Selective clock gating by using wasting toggle rate. Search on Bibsonomy EIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
68Eli Arbel, Oleg Rokhlenko, Karen Yorav SAT-based synthesis of clock gating functions using 3-valued abstraction. Search on Bibsonomy FMCAD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
68Martin Saint-Laurent, Animesh Datta A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF clock gater, clock gating cell, local clock buffer, set-reset latch
65Monica Donno, Enrico Macii, Luca Mazzoni Power-aware clock tree planning. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF clock tree synthesis and routing, physical design and optimization, low-power design, digital design
64Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao Clock gating effectiveness metrics: Applications to power optimization. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
61Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
59Nilanjan Banerjee, Kaushik Roy 0001, Hamid Mahmoodi-Meimand, Swarup Bhunia Low power synthesis of dynamic logic circuits using fine-grained clock gating. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
59Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
55Pietro Babighian, Luca Benini, Enrico Macii A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
55Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
55Wael El-Essawy, David H. Albonesi, Balaram Sinharoy A microarchitectural-level step-power analysis tool. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise
55Hai Li 0001, Swarup Bhunia, Yiran Chen 0001, T. N. Vijaykumar, Kaushik Roy 0001 Deterministic Clock Gating for Microprocessor Power Reduction. Search on Bibsonomy HPCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
51Jun Seomun, Insup Shin, Youngsoo Shin Synthesis and implementation of active mode power gating circuits. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF active leakage, active-mode power gating, low power
51Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
50Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng Predicting the worst-case voltage violation in a 3D power network. Search on Bibsonomy SLIP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF worst case violation prediction, integer linear programming, leakage, clock gating, power networks
50Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi 0001, Takayasu Sakurai Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Nainesh Agarwal, Nikitas J. Dimopoulos Power efficient rapid hardware development using CoDel and automated clock gating. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Xunwei Wu, Massoud Pedram Low power sequential circuit design by using priority encoding and clock gating. Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
50Jens Brandt 0001, Klaus Schneider 0001, Sumit Ahuja, Sandeep K. Shukla The Model Checking View to Clock Gating and Operand Isolation. Search on Bibsonomy ACSD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF operand isolation, model checking, clock gating
50Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori Low-Power Design of 90-nm SuperH Processor Core. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
48Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou Energy Recovering ASIC Design. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Qiang Wang, Subodh Gupta, Jason Helge Anderson Clock power reduction for virtex-5 FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
47Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang Power Consumption Analysis of Embedded Multimedia Application. Search on Bibsonomy ICESS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Amar A. Rasheed, Hacer Varol, Mohamed Baza Clock Gating-Assisted Malware (CGAM): Leveraging Clock Gating On ARM Cortex M* For Attacking Subsystems Availability. Search on Bibsonomy ISDFS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
45Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
45Eric L. Hill, Mikko H. Lipasti Stall cycle redistribution in a transparent fetch pipeline. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF pipeline gating, microarchitecture, dynamic power, instruction fetch
45Yan Luo, Jia Yu 0008, Jun Yang 0002, Laxmi N. Bhuyan Conserving network processor power consumption by exploiting traffic variability. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF scheduling, low power, Network processor, clock gating
42Ramkumar Jayaseelan, Tulika Mitra Dynamic thermal management via architectural adaptation. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF architecture adaptation, dynamic thermal management
41M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mohamed Abdel-Moneum, Mark M. Tehranipoor O'clock: lock the clock via clock-gating for SoC IP protection. Search on Bibsonomy DAC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
41Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Low power, ASIP, ECG, Clock gating, Wireless sensor node
41Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin Speculative software management of datapath-width for energy optimization. Search on Bibsonomy LCTES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating
41Juanjo Noguera, Rosa M. Badia System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF reconfigurable computing, dynamic scheduling, clock-gating, frequency scaling, power-performance trade-offs
41Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster Synchronous Interlocked Pipelines. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF progressive stalls, synchronous, Pipeline, asynchronous, clock gating, elastic, interlocked
39Arjun Rajagopal Clock tree design challenges for robust and low power design. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF NBTI, IR drop
39Jindrich Zejda, Paul Frain General framework for removal of clock network pessimism. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron
37Wanping Zhang, Yi Zhu 0002, Wenjian Yu, Ling Zhang, Rui Shi 0003, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki An automated runtime power-gating scheme. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37David M. Brooks, Margaret Martonosi Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Songyao Tan, Yue Yin, Hanjun Jiang, Zhihua Wang 0001 A 0.7-V Clock-gating Cell with Power Gating Technology and 1.56-pA Sleep Power. Search on Bibsonomy ICTA The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
37Li Li, Ken Choi, Haiqing Nan Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
37Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. Search on Bibsonomy PATMOS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
37Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin Pulser gating: A clock gating of pulsed-latch circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
37Li Li, Ken Choi, Haiqing Nan Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. Search on Bibsonomy ISQED The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
35Aida Todri, Malgorzata Marek-Sadowska A study of reliability issues in clock distribution networks. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero Clock gate on abort: Towards energy-efficient hardware Transactional Memory. Search on Bibsonomy IPDPS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
32Jae-Gon Lee, Younsik Choi, Hoyeon Jeon, Jong-Jin Lee, Dongsuk Shin Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
32Jae-Gon Lee, Hoyeon Jeon, Younsik Choi, Ahchan Kim Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC. Search on Bibsonomy ISSCC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
32Wei-Kai Cheng, Jui-Hung Hung, Yi-Hsuan Chiu Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
32Jianfeng Liu, Mi-Suk Hong, Kyung Tae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi, Abhishek Ranjan Clock domain crossing aware sequential clock gating. Search on Bibsonomy DATE The full citation details ... 2015 DBLP  BibTeX  RDF
32Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng Co-synthesis of data paths and clock control paths for minimum-period clock gating. Search on Bibsonomy DATE The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
32Hoi-Jin Lee, Jong-Woo Kim, Tae Hee Han, Jae-Cheol Son, Jeong-Taek Kong, Bai-Sun Kong Low-power dual-supply clock networks with clock gating and frequency doubling. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
32Shih-Hsu Huang, Chia-Ming Chang 0002, Wen-Pin Tu, Song-Bin Pan Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. Search on Bibsonomy ASP-DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
32Roni Wiener, Gila Kamhi, Moshe Y. Vardi Intelligate: Scalable Dynamic Invariant Learning for Power Reduction. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32José C. Monteiro 0001, Arlindo L. Oliveira Implicit FSM decomposition applied to low-power design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32José C. Monteiro 0001, Arlindo L. Oliveira Finite State Machine Decomposition For Low Power. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF system-on-chip test, testing embedded core, intellectual property test
31Gustavo R. Wilke, Rajeev Murgai Design and Analysis of "Tree+Local Meshes" Clock Architecture. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
27Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. Search on Bibsonomy SAMOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
27Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt System level power estimation methodology with H.264 decoder prediction IP case study. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
27Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner 42% power savings through glitch-reducing clocking strategy in a hearing aid application. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Howard Chen 0001, Daniel L. Ostapko Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Wai-Kwong Lee, Chi-Ying Tsui Finite state machine partitioning for low power. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF C2R, Hardware Coprocessor, Software Algorithms, High Level Synthesis, Clock-gating, Power Reduction
27P. Subramanian, Jagonda Patil, Manish Kumar Saxena FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications. Search on Bibsonomy IWCMC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
27Andrew Herdrich, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell, Vineet Chadha, Jaideep Moses Rate-based QoS techniques for cache/memory in CMP platforms. Search on Bibsonomy ICS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF p-states, performance differentiation, t-states, cache, memory, rate control, qos, clock gating, frequency scaling, dvfs
27Wei-Chung Chao, Wai-Kei Mak Low-power gated and buffered clock network construction. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low power, buffer, clock gating, Clock tree, zero-skew
27Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto Power-efficient LDPC code decoder architecture. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FIFO buffer, LDPC decoder, intermediate message compression technique, message-passing schedule, clock gating
27Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau Aggregating processor free time for energy reduction. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF processor free time, embedded systems, aggregation, clock gating, code transformation, energy reduction
27Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz Experimental measurement of a novel power gating structure with intermediate power saving mode. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
27Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson Design and implementation of the POWER5 microprocessor. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF POWER5, simultaneous multi-threading (SMT), clock gating, power reduction, microprocessor design, temperature sensor
27Sandeep Kumar Goel, Bart Vermeulen Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
27Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel Understanding and minimizing ground bounce during mode transition of power gating structures. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
27Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg A case for dynamic pipeline scaling. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating
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