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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 193 publication records. Showing 193 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
82 | Tamer Cakici, Keejong Kim, Kaushik Roy 0001 |
FinFET Based SRAM Design for Low Standby Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 127-132, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
62 | Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak |
Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 253-258, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
62 | Brian Swahn, Soha Hassoun |
METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 121-126, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
61 | Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu |
Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (4) ![In: Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part IV, pp. 227-234, 2007, Springer, 978-3-540-72589-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
computational statistics, SRAM, modeling and simulation, FinFET |
42 | Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi |
High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 306-307, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
42 | Sushant Mittal, Aneesh Nainani, M. C. Abraham, Saurabh Lodha, Udayan Ganguly |
Enhanced Circuit Densities in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1604.04454, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
41 | Anish Muttreja, Niket Agarwal, Niraj K. Jha |
CMOS logic design with independent-gate FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 560-567, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Brian Swahn, Soha Hassoun |
Electro-Thermal Analysis of Multi-Fin Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 816-829, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Sherif A. Tawfik, Volkan Kursun |
Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 311-316, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar Gupta |
Device/circuit interactions at 22nm technology node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 97-102, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs |
21 | Qamar-Ud-Din Memon, Saif-Ur Rehman, Muhammad Adil Bashir, Noor Muhammad Memon, Mohd Anul Haq, Sultan Alharby, Ahmed Alhussen, Ateeq Ur Rehman 0002 |
An Efficient Technique to Simulate the AC/DC Parameters of Trigate FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 14238-14247, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Elias de Almeida Ramos, Ricardo Reis 0001 |
Comparing the Effects of Process Variability in FinFETs and CNFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 15th IEEE Latin America Symposium on Circuits and Systems, LASCAS 2024, Punta del Este, Uruguay, February 27 - March 1, 2024, pp. 1-5, 2024, IEEE, 979-8-3503-8122-1. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Ki-Sik Im |
Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 10384-10389, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam |
Design Automation of Series Resonance Clocking in 14-nm FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(12), pp. 7549-7579, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Huifan Zhang, Youliang Jing, Pingqiang Zhou |
Machine Learning-Based Device Modeling and Performance Optimization for FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(4), pp. 1585-1589, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Chengxu Wang, Hao Yu, Yichen Wang, Zichong Zhang, Xiangshui Miao, Xingsheng Wang |
Modeling and physical mechanism analysis of the effect of a polycrystalline-ferroelectric gate on FE-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 66(5), May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch |
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Open J. Circuits Syst. ![In: IEEE Open J. Circuits Syst. 4, pp. 258-270, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Rashi Chaudhary, Rajesh Saha |
Impact of self-heating on RF/analog and linearity parameters of DMG FinFETs in underlap and overlap configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 135, pp. 105765, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Po-Chih Chen, Yi-Ting Wu, Meng-Hsueh Chiang |
Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 73-76, 2023, IEEE, 979-8-3503-0423-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Yiming Qu, Chu Yan, Xinwei Yu, Yaru Ding, Yi Zhao |
GHz Cycle-to-Cycle Variation in Ultra-scaled FinFETs: From the Time-Zero to the Aging States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-6, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Zuoyuan Dong, Zixuan Sun, Xin Yang, Xiaomei Li, Yongkang Xue, Chen Luo, Puyang Cai, Zirui Wang, Shuying Wang, Yewei Zhang, Chaolun Wang, Pengpeng Ren, Zhigang Ji, Xing Wu 0005, Runsheng Wang, Ru Huang |
Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Y. Kikuchi, M. Tomita, T. Hayashi, H. Chiba, T. Ogita, T. Okawa, K. Nishida, M. Sugimoto, D. Yoneyama, T. Umeki, H. Oishi, S. Miyake, K. Hiramatsu, H. Kumano, H. Kawashima, N. Yamada, M. Tamura, H. Ohnuma, K. Tatani |
Noise Performance Improvements of 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Non-doped Pixel-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Jing-Yuan Wu, Mu-Yu Chen, Edward. Yi Chang |
Inversion-Mode InGaAs FinFETs for Logic and RF Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-3, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Jianwen Lin, Linlin Cai, Yutao Chen, Haoyu Zhang, Wangyong Chen |
Machine Learning-Assisted Single-Event Transient Model of 12nm FinFETs for Circuit-Level Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Zhongjie Ren, Hsien-Chih Huang, Hanwool Lee, Clarence Chan, Henry C. Roberts, Xihang Wu, Aadil Wassem, Wenjuan Zhu, Xiuling Li |
$\beta$-Ga2O3 FinFETs by MacEtch: temperature dependent I-V characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2023, Santa Barbara, CA, USA, June 25-28, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-2310-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Vibhu, Sparsh Mittal, Vivek Kumar |
Machine Learning-based model for Single Event Upset Current Prediction in 14nm FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-4678-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Antonio Calomarde, Salvador Manich, Antonio Rubio 0001, Francisco Gámiz |
Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 47169-47178, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi |
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 284-285, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Rajat Butola, Yiming Li 0005, Sekhar Reddy Kola |
Machine Learning Approach to Characteristic Fluctuation of Bulk FinFETs Induced by Random Interface Traps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9466-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Surila Guglani, Avirup Dasgupta, Ming-Yen Kao, Chenming Hu, Sourajeet Roy |
Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2022, Columbus, OH, USA, June 26-29, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9883-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Shivendra Singh Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan |
Self-Heating characterization and modeling of 5nm technology node FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2022, Columbus, OH, USA, June 26-29, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9883-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Qamar D. Memon, Umer F. Ahmed, Muhammad Mansoor Ahmed |
A Unified Depletion/Inversion Model for Heterojunction Trigate FinFETs DC Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 89768-89777, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Huan Liu, Genquan Han, Jiuren Zhou, Yan Liu, Yue Hao |
High mobility germanium-on-insulator p-channel FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 64(4), 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Ravi Goel, Weike Wang, Yogesh Singh Chauhan |
Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 110, pp. 105020, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Câncio Monteiro, Yasuhiro Takahashi |
Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 21(24), pp. 8302, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Jesús A. del Alamo, Xiaowei Cai, Xin Zhao, Alon Vardi, Jesús Grajal |
Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 51st IEEE European Solid-State Device Research Conference, ESSDERC 2021, Grenoble, France, September 13-22, 2021, pp. 203-206, 2021, IEEE, 978-1-6654-3748-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Sachin Bhat, Mingyu Li, Sounak Shaun Ghosh, Sourabh Kulkarni, Csaba Andras Moritz |
SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021, pp. 176-181, 2021, IEEE, 978-1-6654-3946-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Longda Zhou, Zhaohao Zhang, Hong Yang, Zhigang Ji, Qianqian Liu, Qingzhu Zhang, Eddy Simoen, Huaxiang Yin, Jun Luo, Anyan Du, Chao Zhao, Wenwu Wang 0006 |
A Fast DCIV Technique for Characterizing the Generation and Repassivation of Interface Traps Under DC/ AC NBTI Stress/Recovery Condition in Si p-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2021, Monterey, CA, USA, March 21-25, 2021, pp. 1-7, 2021, IEEE, 978-1-7281-6893-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Hao Chang, Longda Zhou, Hong Yang, Zhigang Ji, Qianqian Liu, Eddy Simoen, Huaxiang Yin, Wenwu Wang 0006 |
Comparative Study on the Energy Distribution of Defects under HCD and NBTI in Short Channel p-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2021, Monterey, CA, USA, March 21-25, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-6893-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Dawei Wang, Tao Liu, Xin Sun, Kun Chen, Jingwen Yang, Chunlei Wu, Min Xu, David Wei Zhang |
Channel Stress Engineering Through Source/Drain Recess Optimization and Its Process Variation Study for 5 nm-node FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Joshua A. Perozek, Ahmad Zubair, Tomás Palacios |
Small-Signal, High Frequency Performance of Vertical GaN FinFETs with fmax = 5.9 GHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2021, Santa Barbara, CA, USA, June 20-23, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-1240-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Jun-Sik Yoon, Rock-Hyun Baek |
Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 189395-189403, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Antonio Calomarde, Antonio Rubio 0001, Francesc Moll, Francisco Gámiz |
Active Radiation-Hardening Strategy in Bulk FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 201441-201449, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Michael A. Turi, José G. Delgado-Frias |
Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(4), pp. 765-769, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | N. Praveen Kumar, B. Stephen Charles, V. Sumalatha |
Implementation of cache memory and fir filter using FINFETs at 22 nm technology for SOC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 77, pp. 103191, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Haiyan Ni, Jianping Hu, Xuqiang Zhang, Haotian Zhu |
The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(7), pp. 2050114:1-2050114:28, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Kirti Bhanushali, Chinmay Tembe, W. Rhett Davis |
Development of a Predictive Process Design kit for15-nm FinFETs: FreePDK15. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.04600, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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21 | Talha Furkan Canan, Savas Kaya, Harsha Chenji, Avinash Karanth |
Reconfigurable Gates with Sub-10nm Ambipolar SB-FinFETs for Logic Locking & Obfuscation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020, pp. 953-956, 2020, IEEE, 978-1-7281-8058-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Vinay C. Patil, Sandip Kundu |
On Leveraging Multi-threshold FinFETs for Design Obfuscation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020, Limassol, Cyprus, July 6-8, 2020, pp. 108-113, 2020, IEEE, 978-1-7281-5775-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Zhiqing Li, Baofu Zhu, Anindya Nath, Meng Miao, Alain Loiseau, You Li, Jeffrey B. Johnson, Souvick Mitra, Robert Gauthier 0002 |
Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-3199-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Yiming Qu, Jiwu Lu, Junkang Li, Zhuo Chen, Jie Zhang, Chunlong Li, Shiuh-Wuu Lee, Yi Zhao |
In-Situ Monitoring of Self-Heating Effect in Aggressively Scaled FinFETs and Its Quantitative Impact on Hot Carrier Degradation Under Dynamic Circuit Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-3199-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Longda Zhou, Qingzhu Zhang, Hong Yang, Zhigang Ji, Zhaohao Zhang, Renren Xu, Huaxiang Yin, Wenwu Wang 0006 |
Comparative Study on the Energy Profile of NBTI-Related Defects in Si and Ferroelectric p-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-3199-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Talha Furkan Canan, Savas Kaya, Avinash Karanth, Ahmed Louri |
4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, Scotland, UK, November 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6044-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu |
Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Ahmad Zubair, Joshua A. Perozek, John Niroula, O. Aktas, V. Odnoblyudov, Tomás Palacios |
First Demonstration of GaN Vertical Power FinFETs on Engineered Substrate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: 2020 Device Research Conference, DRC 2020, Columbus, OH, USA, June 21-24, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-7047-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Umer Farooq Ahmed, Muhammad Mansoor Ahmed |
An analytical model to assess DC characteristics of independent gate Si FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 27(4), pp. 2456-2465, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek |
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 75762-75767, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jinsu Jeong, Hyeok Yun, Bohyeon Kang, Rock-Hyun Baek |
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 172290-172295, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Wen-Teng Chang, Shih-Wei Lin, Min-Cheng Chen, Wen-Kuan Yeh |
Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 102-C(6), pp. 429-434, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Umer F. Ahmed, Muhammad Mansoor Ahmed, Qamar D. Memon |
Non-linear compact model for FinFETs output characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(8), pp. 1249-1254, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Maneesha Rupakula, Junrui Zhang, Francesco Bellando, Fabien Wildhaber, Clarissa Convertino, Heinz Schmid, Kirsten E. Moselund, Adrian Mihai Ionescu |
Monolithically integrated catalyst-free High Aspect Ratio InAs-On-Insulator (InAsOI) FinFETs for pH sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 49th European Solid-State Device Research Conference, ESSDERC 2019, Cracow, Poland, September 23-26, 2019, pp. 106-109, 2019, IEEE, 978-1-7281-1539-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Hai Jiang 0005, Hyun-Chul Sagong, Jinju Kim, Junekyun Park, Sangchul Shin, Sangwoo Pae |
Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, pp. 1-5, 2019, IEEE, 978-1-5386-9504-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | M. Iqbal Mahmud, Amit Gupta, Maria Toledano-Luque, N. Rao Mavilla, J. Johnson, P. Srinivasan 0002, A. Zainuddin, S. Rao, Salvatore Cimino, Byoung Min, Tanya Nigam |
Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, pp. 1-6, 2019, IEEE, 978-1-5386-9504-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Alexander Makarov, Ben Kaczer, Philippe Roussel, Adrian Vaisman Chasin, Alexander Grill, Michiel Vandemaele, Geert Hellings, Al-Moatasem El-Sayed, Tibor Grasser, Dimitri Linten, Stanislav Tyaginov |
Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, pp. 1-7, 2019, IEEE, 978-1-5386-9504-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Narendra Parihar, Uma Sharma, Richard G. Southwick, Miaomiao Wang 0006, James H. Stathis, Souvik Mahapatra |
On the Frequency Dependence of Bulk Trap Generation During AC Stress in Si and SiGe RMG P-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, pp. 1-8, 2019, IEEE, 978-1-5386-9504-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Xiaoxiao Xu, Jianping Hu, Shengwei Ke |
Negative Capacitance Dual-Threshold Independent Gate FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Anton Sorokin, Nikolay Ryzhenko |
SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019, pp. 159-164, 2019, ACM, 978-1-4503-6252-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Ran Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-Yan Zhang, Yi Zhao |
Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | U. Rana, D. P. Brunco, S. Raman, Dina H. Triyoso, M. W. Stoker, J. B. Johnson, Luigi Pantisano, K. D. Seo, M. Zhao, A. Reznicek, R. Krishnan, B. Moser, J. Freeman, L. Jang, Evgeny Kaganer |
High Performance and Yield for Super Steep Retrograde Wells (SSRW) by Well Implant / Si-based Epitaxy on Advanced Technology FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2019, Ann Arbor, MI, USA, June 23-26, 2019, pp. 251-252, 2019, IEEE, 978-1-7281-2111-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | T. Nagateja, Avireni Srinivasulu, Dipankar Pal |
RF Harvesting System for Low-Power Applications Using FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2019, Las Vegas, NV, USA, January 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-5386-7910-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Armineh Arasteh, Mohammad Hossein Moaiyeri, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh |
An energy and area efficient 4: 2 compressor based on FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 60, pp. 224-231, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Tiansong Cui, Ji Li 0006, Yanzhi Wang, Shahin Nazarian, Massoud Pedram |
An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 6(2), pp. 172-183, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Scott R. Stiffler, Ravikumar Ramachandran, W. Kirklen Henson, Noah Zamdmer, Kevin McStay, Giuseppe La Rosa, Kevin M. Boyd, Sungjae Lee, Claude Ortolland, Paul C. Parries |
Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 62(2/3), pp. 11:1-11:7, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Lei Shen, Shaoyan Di, Longxiang Yin, Xiaoyan Liu, Gang Du |
Calibration of drift-diffusion model in quasi-ballistic transport region for FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 61(6), pp. 062406:1-062406:8, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Longxiang Yin, Lei Shen, Hai Jiang, Gang Du, Xiaoyan Liu |
Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 61(6), pp. 062401:1-062401:9, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Roya Dibaj, Dhamin Al-Khalili, Maitham Shams |
Gate Oxide Short Defect Model in FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 34(3), pp. 351-362, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Fu-Yuan Tuan, Chii-Wen Chen, Mu-Chun Wang, Wen-Shiang Liao, Shea-Jue Wang, Shou-Kong Fan, Wen-How Lan |
Thermal stress probing the channel-length modulation effect of nano n-type FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 83, pp. 260-270, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Ivo Vogt, Tomonori Nakamura, B. Motamedi, Christian Boit |
Device characterization of 16/14 nm FinFETs for reliability assessment with infrared emission spectra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 11-15, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Ivo Vogt, Tomonori Nakamura, Ingrid De Wolf, Christian Boit |
Detection of failure mechanisms in 24-40 nm FinFETs with (spectral) photon emission techniques using InGaAs camera. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 334-338, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Mariusz Zubert, Tomasz Raszkowski, Agnieszka Samson, Piotr Zajac |
Methodology of determining the applicability range of the DPL model to heat transfer in modern integrated circuits comprised of FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 91, pp. 139-153, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Erry Dwi Kurniawan, Hao Yang, Chia-Chou Lin, Yung-Chun Wu |
Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 83, pp. 254-259, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Clarissa Convertino, Cezar B. Zota, Daniele Caimi, Marilyne Sousa, L. Czornomaz |
InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018, pp. 162-165, 2018, IEEE, 978-1-5386-5401-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Theano A. Karatsori, K. Bennamane, Christoforos G. Theodorou, L. Czornomaz, Jean Fompeyrine, Cezar B. Zota, Clarissa Convertino, Gérard Ghibaudo |
Static and Low Frequency Noise Characterization of InGaAs MOSFETs and FinFETs on Insulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018, pp. 166-169, 2018, IEEE, 978-1-5386-5401-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Yunus Kelestemur, Soumyasanta Laha, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri |
Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 332-335, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Jacopo Franco, Ben Kaczer, Adrian Vaisman Chasin, Erik Bury, Dimitri Linten |
Hot electron and hot hole induced degradation of SiGe p-FinFETs studied by degradation maps in the entire bias space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 5, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Shaofeng Guo, Zhenghan Lin, Runsheng Wang, Zexuan Zhang, Zhe Zhang, Yangyuan Wang, Ru Huang |
Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 6-1, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | I. K. Chen, S. C. Chen, S. Mukhopadhyay, D. S. Huang, J. H. Lee, Y. S. Tsai, Ryan Lu, Jun He |
The physical mechanism investigation of off-state drain bias TDDB and its implication in advance HK/MG FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 4, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri |
10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pp. 577-580, 2018, IEEE, 978-1-5386-9562-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Venkatesh Srinivasan, Stephane Le Tuai, Tai-Cheng Lee |
F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 505-507, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Tingfeng Yang, Jianping Hu, Wenjing Bai |
Analysis and Simulation of Negative Capacitance Independent Multi-Gate FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | D. A. J. Millar, X. Li, U. Peralagu, M. J. Steer, I. M. Pavey, Guilherme Gaspar, M. Schmidt, P. K. Hurley, I. G. Thayne |
High Aspect Ratio Junctionless InGaAs FinFETs Fabricated Using a Top-Down Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: 76th Device Research Conference, DRC 2018, Santa Barbara, CA, USA, June 24-27, 2018, pp. 1-2, 2018, IEEE, 978-1-5386-3027-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Ke Han, Guohui Qiao, Zhongliang Deng, Qingbo Li, Huashuai Xing |
The optimal geometry parameters and impact of parasitic capacitance and resistance of sub-14nm SOI multi-fin FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Fuzzy Syst. ![In: J. Intell. Fuzzy Syst. 33(5), pp. 2699-2709, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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21 | Shilpa Saxena, Rajesh Mehra |
Low-power and high-speed 13T SRAM cell using FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 11(3), pp. 250-255, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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21 | Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar |
Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 11(1), pp. 80-88, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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21 | Nanditha P. Rao, Madhav P. Desai |
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1706.03315, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
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21 | Luca Donetti, Carlos Sampedro 0002, Francisco Javier García Ruiz, Andres Godoy, Francisco Gámiz |
Three-dimensional multi-subband simulation of scaled FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017, pp. 180-183, 2017, IEEE, 978-1-5090-5978-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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21 | F. M. Bufler, Kenichi Miyaguchi, Thomas Chiarella, N. Horiguchi, Anda Mocuta |
On the ballistic ratio in 14nm-Node FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017, pp. 176-179, 2017, IEEE, 978-1-5090-5978-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Wei-feng Lü, Mi Lin, Haipeng Zhang |
Investigation on Gate Capacitances Fluctuation Due to Work-Function Variation in Metal-Gate FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSDM ![In: Fuzzy Systems and Data Mining III - Proceedings of FSDM 2017 [Hualien, Taiwan, November 2017]., pp. 398-403, 2017, IOS Press, 978-1-61499-827-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Haotian Zhu, Jianping Hu, Huishan Yang, Yang Xiong, Tingfeng Yang |
A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6462-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri |
Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 100-103, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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