Search results for "Stuck-at-fault"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model
72	Sumit Ghosh, Tapan J. Chakraborty	On behavior fault modeling for digital designs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model
68	Irith Pomeranz, Sudhakar M. Reddy	Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
66	Irith Pomeranz, Sudhakar M. Reddy	Test sequences to achieve high defect coverage for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
65	Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient
62	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
61	Baris Arslan, Alex Orailoglu	Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
55	Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche	Test Challenges in Nanometer Technologies.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	circuit marginality testing, process marginality testing, defect based testing, path delay testing
53	Sreejit Chakravarty, Yiming Gong	Voting model based diagnosis of bridging faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure
53	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
53	Meine van der Meulen	Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV.	FMCAD	2002	DBLP DOI BibTeX RDF
51	Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren	Quantitative Analysis of In-Field Defects in Image Sensor Arrays.	DFT	2007	DBLP DOI BibTeX RDF
50	Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara	A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms.	DATE	2003	DBLP DOI BibTeX RDF
49	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Multiple Faults: Modeling, Simulation and Test.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	ATPG Modeling, Fault Modeling, Multiple Fault
49	Joseph L. A. Hughes	Multiple fault detection using single fault test sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
48	Hisashi Kondo, Kwang-Ting Cheng	Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pseudo Stuck-at Fault, Sequential ATPG, Vector compaction, Test, Fault model, IDDQ, Leakage Fault
47	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Combinational automatic test pattern generation for acyclic sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
47	Tapan J. Chakraborty, Vishwani D. Agrawal	Simulation of at-speed tests for stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
46	T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu	On the fault diagnosis in the presence of unknown fault models using pass/fail information.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
46	Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu	Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
44	Joseph L. A. Hughes, Edward J. McCluskey	Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets.	ITC	1986	DBLP BibTeX RDF
43	Irith Pomeranz, Sudhakar M. Reddy	A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy.	DATE	2008	DBLP DOI BibTeX RDF
43	Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi	False-Path Removal Using Delay Fault Simulation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal
43	Wen-Ben Jone, Patrick H. Madden	Multiple fault testing using minimal single fault test set for fanout-free circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
43	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
42	Robert C. Aitken	Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage.	VTS	1999	DBLP DOI BibTeX RDF
42	Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs	Dynamic diagnosis of sequential circuits based on stuck-at faults.	VTS	1996	DBLP DOI BibTeX RDF	dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm
42	Tapan J. Chakraborty, Vishwani D. Agrawal	Design for high-speed testability of stuck-at faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
42	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	On test coverage of path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
41	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
41	Niraj K. Jha	Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
41	Xiao Sun 0002, Carmie Hull	Functional Verification Coverage vs. Physical Stuck-at Fault Coverage.	DFT	1998	DBLP DOI BibTeX RDF	functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
40	Piotr R. Sidorowicz	Modeling and Testing Transistor Faults in Content-Addressable Memories.	MTDT	1999	DBLP DOI BibTeX RDF
40	Gang-Min Park, Hoon Chang	An extended march test algorithm for embedded memories.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	efficient test algorithm, BIST architecture, neighborhood pattern sensitive fault, background data, word-oriented memory testing, extended march test algorithm, stuck-at fault, transition fault, embedded memories, integrated memory circuits, coupling fault
40	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
40	Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty	Path Delay Fault Simulation on Large Industrial Designs.	VTS	2006	DBLP DOI BibTeX RDF
40	Karim Arabi, Hassan Ihs, Christian Dufaza, Bozena Kaminska	Digital oscillation-test method for delay and stuck-at fault testing of digital circuits.	ITC	1998	DBLP DOI BibTeX RDF
39	Alvin Jee, F. Joel Ferguson	A methodolgy for characterizing cell testability.	VTS	1997	DBLP DOI BibTeX RDF	cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects
39	Irith Pomeranz, Sudhakar M. Reddy	On n-detection test sequences for synchronous sequential circuits343.	VTS	1997	DBLP DOI BibTeX RDF	n-detection test sequences, stuck-at fault detection, test generation procedures, logic testing, fault simulation, synchronous sequential circuits, defect coverages
39	Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers	Deterministic Logic BIST for Transition Fault Testing.	ETS	2006	DBLP DOI BibTeX RDF	Deterministic logic BIST, delay test
39	Avik Chakraborty	Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.	VLSI Design	2005	DBLP DOI BibTeX RDF	Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
38	Niraj K. Jha	Testing for multiple faults in domino-CMOS logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
38	Jan Torben Weinkopf, Klaus Harbich, Erich Barke	Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models.	FPL	2006	DBLP DOI BibTeX RDF
38	Yiming Gong, Sreejit Chakravarty	Locating bridging faults using dynamically computed stuck-at fault dictionaries.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
37	Jing-Yang Jou	An effective BIST design for PLA.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register
37	Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams	On the decline of testing efficiency as fault coverage approaches 100%.	VTS	1995	DBLP DOI BibTeX RDF	single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
36	Ugur Kalay, Douglas V. Hall, Marek A. Perkowski	A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set
36	Seiji Kajihara, Tsutomu Sasao	On the Adders with Minimum Tests.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders
36	Audhild Vaaje	Theorems for Fault Collapsing in Combinational Circuits.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	Boolean function, combinational circuit, monotonic function, fault collapsing
36	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.	FPL	1998	DBLP DOI BibTeX RDF
35	Leendert M. Huisman	Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
35	Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin	Redundancy Identification Using Transitive Closure.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
35	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
33	Irith Pomeranz, Sudhakar M. Reddy	The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality.	VLSI Design	2009	DBLP DOI BibTeX RDF
33	Lei Fang 0002, Michael S. Hsiao	Bilateral Testing of Nano-scale Fault-Tolerant Circuits.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Bilateral fault model, Fault-tolerant, ATPG, Nanoelectronics
33	Lei Fang 0002, Michael S. Hsiao	Bilateral Testing of Nano-scale Fault-tolerant Circuits.	DFT	2006	DBLP DOI BibTeX RDF
33	Nilanjan Mukherjee 0001	Improving Test Quality Using Test Data Compression.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
33	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
32	Shweta Chary, Michael L. Bushnell	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
32	Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul	A test evaluation technique for VLSI circuits using register-transfer level fault modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
32	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling.	DFT	2002	DBLP DOI BibTeX RDF
32	Vladimir Hahanov, Anna Babich	Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices.	DSD	2001	DBLP DOI BibTeX RDF
32	Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang	Novel techniques for improving testability analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns
32	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck	On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple stuck-at fault simulation, multiple domain simulation, comparative simulation, MDCCS, discrete event concurrent simulation, CPU time efficiency, digital logic fault simulation, fault diagnosis, logic testing, discrete event simulation, circuit analysis computing, fault location, concurrent engineering
32	Mitrajit Chatterjee, Dhiraj K. Pradhan	A novel pattern generator for near-perfect fault-coverage.	VTS	1995	DBLP DOI BibTeX RDF	near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault
31	Yung-Chih Chen, Chun-Yao Wang	An Implicit Approach to Minimizing Range-Equivalent Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
30	Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar	Defect-Oriented Fault Simulation and Test Generation in Digital Circuits.	ISQED	2001	DBLP DOI BibTeX RDF
29	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
29	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck	A multiple domain environment for efficient simulation.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	multiple domain environment, efficient simulation, concurrent simulation methodology, digital logic experimentation, multiple experiment environment, independent experiments, parallel hardware, digital logic simulators, signature paths, multiple experiment algorithms, function list, dynamic interactions, exhaustive simulation problem, Multiple Stuck-at Fault simulations, logic CAD, coverage analysis, digital logic
29	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
29	Fidel Muradali, Janusz Rajski	A self-driven test structure for pseudorandom testing of non-scan sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
29	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
29	Fadi Y. Busaba, Parag K. Lala	A graph coloring based approach for self-checking logic circuit design.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	logic circuit design, bidirectional error, residue weights assignments, output lines, errors identification, graph theory, logic testing, integrated circuit testing, logic design, error detection, error detection, automatic testing, graph coloring, fault location, integrated logic circuits, graph colouring, self-checking, residue codes, single stuck-at fault
29	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
29	Piet Engelke, Bernd Becker 0001, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian	SUPERB: Simulator utilizing parallel evaluation of resistive bridges.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PPSFP, SPPFP, fault mapping, Resistive bridging faults, bridging fault simulation
29	Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu	MRAM Defect Analysis and Fault Modeli.	ITC	2004	DBLP DOI BibTeX RDF
29	Ramesh C. Tekumalla, Scott Davidson 0001	On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.	ITC	2002	DBLP DOI BibTeX RDF
29	Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth	Generating Tests for Delay Faults in Nonscan Circuits.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
28	Hamidreza Hashempour, Fabrizio Lombardi	Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs.	DATE	2007	DBLP DOI BibTeX RDF	CNTFET, fault detection, nanotechnology, carbon nanotube, defect modeling, CNT
28	Ketan N. Patel, John P. Hayes, Igor L. Markov	Fault testing for reversible circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
28	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Carry Logic Modules of SRAM-based FPGAs.	MTDT	2001	DBLP DOI BibTeX RDF
28	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
27	Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Faizal Karim, Konrad Walus, André Ivanov	On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.	DFT	2007	DBLP DOI BibTeX RDF
27	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Fault tolerance, error checking, high-speed arithmetic
27	Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim	Fault Analysis of the Multiple Valued Logic Using Spectral Method.	ISMVL	2000	DBLP DOI BibTeX RDF	spectral domain, bridging fault, multiple valued logic, fault analysis
27	João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves	A methodology for testability enhancement at layout level.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	physical design rules for testability, simulation, fault modeling, testability analysis
27	Hyein Shin, Myeonggu Kang, Lee-Sup Kim	Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
27	Lorena Anghel, Anna Bernasconi 0001, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu	Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model.	LATS	2019	DBLP DOI BibTeX RDF
27	Jan Schat	On the relationship between stuck-at fault coverage and transition fault coverage.	DATE	2009	DBLP DOI BibTeX RDF
27	Kentaroh Katoh, Kazuteru Namba, Hideo Ito	Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.	IPSJ Trans. Syst. LSI Des. Methodol.	2008	DBLP DOI BibTeX RDF
27	Jan Schat	Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns.	DDECS	2008	DBLP DOI BibTeX RDF
27	Jue Wu, Elizabeth M. Rudnick	Bridge fault diagnosis using stuck-at fault simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
27	Janak H. Patel	Stuck-at fault: a fault model for the next millennium.	ITC	1998	DBLP DOI BibTeX RDF
27	Joseph L. A. Hughes, Edward J. McCluskey	An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets.	ITC	1984	DBLP BibTeX RDF
26	Irith Pomeranz, W. Kent Fuchs	A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
26	Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel	Sequential circuit testability enhancement using a nonscan approach.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
26	Weiwei Mao, Ravi K. Gulati	Quietest: A methodology for selecting IDDQ test vectors.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	weak faults, I DDQ testing, Leakage faults
25	Zhigang Jiang, Sandeep K. Gupta 0001	Threshold testing: Covering bridging and other realistic faults.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
24	Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001	Systematic Software-Based Self-Test for Pipelined Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
24	Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.	VLSI Design	2008	DBLP DOI BibTeX RDF	Missing-gate faults, quantum computing, reversible logic, testable design, universal test set