Search results for "gate-arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
74	Robert C. Minnick	A Survey of Microcellular Research.	J. ACM	1967	DBLP DOI BibTeX RDF
72	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
72	Wei-Kang Huang, Fabrizio Lombardi	An approach for testing programmable/configurable field programmable gate arrays.	VTS	1996	DBLP DOI BibTeX RDF	behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
68	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
67	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
61	Yen-Tai Lai, Ping-Tsung Wang	Hierarchical interconnection structures for field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
57	Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
50	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
50	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology.	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
50	Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001	Re-engineering of timing constrained placements for regular architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging
50	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
50	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
48	Shinichi Kato, Minoru Watanabe	Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI.	SAMOS	2009	DBLP DOI BibTeX RDF
47	Mao Nakajima, Daisaku Seto, Minoru Watanabe	A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time.	IPDPS	2008	DBLP DOI BibTeX RDF
47	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
46	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
46	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	Improving quantum circuit dependability with reconfigurable quantum gate arrays.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	accuracy threshold, reconfigurable quantum gate arrays, coding
46	Amit Chowdhary, John P. Hayes	General technology mapping for field-programmable gate arrays based on lookup tables.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
46	Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois 0001	The Design of RPM: An FPGA-based Multiprocessor Emulator.	FPGA	1995	DBLP DOI BibTeX RDF	field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers
46	Stephen D. Scott 0001, Ashok Samal, Sharad C. Seth	HGA: A Hardware-Based Genetic Algorithm.	FPGA	1995	DBLP DOI BibTeX RDF	performance acceleration, performance evaluation, field programmable gate arrays, function optimization, parallel genetic algorithms
43	Shantanu Chakrabartty, Gert Cauwenberghs	Fixed-current method for programming large floating-gate arrays.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
43	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
43	Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley	Efficient tiling patterns for reconfigurable gate arrays.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA hexagonal octagonal, tiling interconnect
43	Pak K. Chan, Martine D. F. Schlag	Parallel placement for field-programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement, analytical placement
43	Peter Suaris, Dongsheng Wang 0012, Pei-Ning Guo, Nan-Chi Chou	A physical retiming algorithm for field programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF
43	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
41	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Design and analysis of FPGA/FPIC switch modules.	ICCD	1995	DBLP DOI BibTeX RDF	FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
41	Mark G. Karpovsky	Multilevel Logical Networks.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	time and space complexity of gate arrays, AND-OR implementations of systems of Boolean functions, gate counts, multilevel logical networks, delays, gate arrays
39	Minoru Watanabe, Fuminori Kobayashi	An Improved Dynamic Optically Reconfigurable Gate Array.	ISVLSI	2005	DBLP DOI BibTeX RDF
39	Robert J. Francis, Jonathan Rose, Kevin Chung	Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays.	DAC	1990	DBLP DOI BibTeX RDF
39	Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi	A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays.	IPDPS	2007	DBLP DOI BibTeX RDF
38	Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
37	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
37	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
37	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: an active glitch minimization technique for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, power minimization
37	Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
37	Jason Helge Anderson, Farid N. Najm, Tim Tuan	Active leakage power optimization for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	optimization, FPGAs, field-programmable gate arrays, low-power design, power, leakage
37	Michael G. Wrighton, André DeHon	Hardware-assisted simulated annealing with application for fast FPGA placement.	FPGA	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation
37	Pedro C. Diniz, Joonseok Park	Data reorganization engines for the next generation of system-on-a-chip FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
37	Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson	A dynamically reconfigurable adaptive viterbi decoder.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
37	Jörg Ritter 0002, Paul Molitor	A pipelined architecture for partitioned DWT based lossy image compression using FPGA's.	FPGA	2001	DBLP DOI BibTeX RDF	embedded zero tree coding, FPGA, field programmable gate arrays, architecture, wavelet transformation, pipelining, Xilinx, lossy image compression
37	Steven J. E. Wilton	A crosstalk-aware timing-driven router for FPGAs.	FPGA	2001	DBLP DOI BibTeX RDF	field-programmable gate arrays, routing algorithms, crosstalk
37	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
37	Amit Chowdhary, John P. Hayes	Technology mapping for field-programmable gate arrays using integer programming.	ICCAD	1995	DBLP DOI BibTeX RDF	Field-programmable gate arrays (FPGAs), technology mapping, mixed integer linear programming (MILP), lookup tables, circuit partitioning
35	Kouhi Shinohara, Minoru Watanabe	Defect tolerance of holographic configurations in ORGAs.	IPDPS	2008	DBLP DOI BibTeX RDF
35	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, dynamic programming, systolic array, throughput optimization, recurrences
34	Michaela E. Amoo, Youngsoo Kim, Vance Alford, Shrikant Jadhav, Naser I. El-Bathy, Clay S. Gloster Jr.	An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
34	Youngsoo Kim, William Harding, Clay S. Gloster Jr., Winser E. Alexander	Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
34	Abdullah Nazma Nowroz, Sherief Reda	Thermal and power characterization of field-programmable gate arrays.	FPGA	2011	DBLP DOI BibTeX RDF
34	Deshanand P. Singh, Stephen Dean Brown	Constrained clock shifting for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
34	Deshanand P. Singh, Stephen Dean Brown	The case for registered routing switches in field programmable gate arrays.	FPGA	2001	DBLP DOI BibTeX RDF
34	John R. Koza, Forrest H. Bennett III, Jeffrey L. Hutchings, Stephen L. Bade, Martin A. Keane, David Andre	Evolving Computer Programs Using Rapidly Reconfigurable Field-Programmable Gate Arrays and Genetic Programming.	FPGA	1998	DBLP DOI BibTeX RDF
34	Vi Cuong Chan, David M. Lewis	Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays.	FPGA	1996	DBLP DOI BibTeX RDF
34	Jouni Isoaho, Arto Nummela, Hannu Tenhunen	Technologies and Utilization fo Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
34	Hartmut Surmann, Ansgar Ungering, Karl Goser	Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
34	Alberto L. Sangiovanni-Vincentelli	Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design.	FPL	1992	DBLP DOI BibTeX RDF
31	John H. Zurawski, J. B. Gosling	Design of High-Speed Digital Divider Units.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	uncommitted logic arrays (gate arrays), Borrow?save subtraction, carry?save addition, digital division, group subtractor, iterative division, digital arithmetic
31	Mao Nakajima, Minoru Watanabe	Fast Optical Reconfiguration of a Nine-Context DORGA.	ARC	2009	DBLP DOI BibTeX RDF
31	Kristian Stevens, Henry Chen, Terry Filiba, Peter L. McMahon, Yun S. Song	Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	genome resequencing, fpga, acceleration, reconfigurable logic
31	A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.	FPGA	2004	DBLP DOI BibTeX RDF
30	Daisaku Seto, Minoru Watanabe	Analysis of retention time under multi-configuration on a DORGA.	SoCC	2008	DBLP DOI BibTeX RDF
30	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
30	Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frédéric Bancel	Securing embedded programmable gate arrays in secure circuits.	IPDPS	2006	DBLP DOI BibTeX RDF
30	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
30	Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti 0001	A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF
30	Jason Cong, Hui Huang 0001	Depth optimal incremental mapping for field programmable gate arrays.	DAC	2000	DBLP DOI BibTeX RDF
30	Julian F. Miller	On the Filtering Properties of Evolved Gate Arrays.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
30	Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson	The yield enhancement of field-programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
30	Jin Hwan Park, H. K. Dai 0001	Reconfigurable hardware solution to parallel prefix computation.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Parallel prefix computation, Field-programmable gate arrays, Pipeline, Dataflow, Reconfigurable hardware
30	Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr V. Kindratenko, Duncan A. Buell	The Promise of High-Performance Reconfigurable Computing.	Computer	2008	DBLP DOI BibTeX RDF	HPRC systems, field-programmable gate arrays, high-performance computing, reconfigurable computing
30	Adam Handzlik, Andrzej Jablonski	"Chameleon" Software Defined Control Platform.	EUROCAST	2007	DBLP DOI BibTeX RDF	Signal processing architectures, control platform development, innovative reprogrammable technology, virtual Programmable Logic Controller, Field Programmable Gate Arrays, IP Core
30	Ahmad Darabiha, W. James MacLean, Jonathan Rose	Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF	Stereo disparity estimation, Frame rate implementation, Reconfigurable hardware implementation, Field Programmable Gate Arrays (FPGAs), Phase correlation
30	Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk	Optimizing Hardware Function Evaluation.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	elementary function approximation, minimax approximation and algorithms, optimization, Computer arithmetic, gate arrays
30	Sai Gopalan, Gayathri Venkataraman, Sabu Emmanuel	FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	cluster maintenance algorithm, VHDL (Very High Speed Integrated Circuit Hardware Description Language), FPGA (Field Programmable Gate Arrays), Mobile ad-hoc networks
30	Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama	FPGA Implementation of Fast Radix 4 Division Algorithm.	IWSOC	2004	DBLP DOI BibTeX RDF	fast division, radix 4 division, quotient selection, Field programmable gate arrays (FPGAs)
30	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, Built-In Self-Test, delay faults
30	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi	A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications.	DELTA	2002	DBLP DOI BibTeX RDF	Fault Tolerance, Field programmable Gate Arrays, Multistage Interconnection Network, Space Applications
30	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
30	Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi	Novel Technique for Testing FPGAs.	DATE	1998	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, testing, reuse, diagnosis
30	Donald L. Hung, Antonio Arsgao, Jorge L. Silva, Eduardo Marques, Karl Hillesland	UB1 - a recurrent neural network based parallel machine for solving simultaneous linear equations.	SBRN	1997	DBLP DOI BibTeX RDF	UB1 recurrent neural network, simultaneous linear equation solving, synchronous execution, field programmable gate arrays, real-time systems, parallel machine, systolic array, neural chips, ring topology, neural net architecture
30	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
30	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
26	Minoru Watanabe, Fuminori Kobayashi	A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory.	FPL	2006	DBLP DOI BibTeX RDF
26	Minoru Watanabe, Fuminori Kobayashi	Power consumption advantage of a dynamic optically reconfigurable gate array.	IPDPS	2006	DBLP DOI BibTeX RDF
26	Minoru Watanabe, Fuminori Kobayashi	A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
26	Mitsuho Seki, Shun'ichi Kobayashi, Munehiro Takubo, Kazuyoshi Kurosawa	A New Floorplan Simultaneously Placing Blocks over Two Logic Layers for Sea-of-gate Gate Arrays.	ISCAS	1993	DBLP BibTeX RDF
26	Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
26	Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna	Memory efficient string matching: a modular approach on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	deep packet classification, fpga, packet filtering
26	Kuen Hung Tsoi, Wayne Luk	Axel: a heterogeneous cluster with FPGAs and GPUs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, heterogeneous cluster
26	David L. Foster, Darrin M. Hanna	Maximizing area-constrained partial fault tolerance in reconfigurable logic.	FPGA	2010	DBLP DOI BibTeX RDF	area-constrained, FPGA
26	Philippa Conmy, Iain Bate	Semi-Automated Safety Analysis for Field Programmable Gate Arrays.	ECBS	2009	DBLP DOI BibTeX RDF
26	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt	FPGA-based front-end electronics for positron emission tomography.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, localization, timing, positron emission tomography
26	David Sheldon, Frank Vahid	Making good points: application-specific pareto-point generation for design space exploration using statistical methods.	FPGA	2009	DBLP DOI BibTeX RDF	configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments
26	Roto Le, Sherief Reda, R. Iris Bahar	High-performance, cost-effective heterogeneous 3D FPGA architectures.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, heterogeneous, 3d ic, switch box, through silicon via
26	Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	HW/SW methodologies for synchronization in FPGA multiprocessors.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, synchronization, multiprocessors
26	Theepan Moorthy, Andy Ye	A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.	FPL	2008	DBLP DOI BibTeX RDF
26	James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington	Creating unique identifiers on field programmable gate arrays using natural processing variations.	FPL	2008	DBLP DOI BibTeX RDF
26	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck	Fpga-based data acquisition system for a positron emission tomography (PET) scanner.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, positron emission tomography
26	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
26	Scott Miller, Mihai Sima, Michael McGuire	Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays.	DSD	2007	DBLP DOI BibTeX RDF