Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Amjad Hajjar, Tom Chen 0001	VLSI Architecture for Real-Time Edge Linking.	IEEE Trans. Pattern Anal. Mach. Intell.	1999	DBLP DOI BibTeX RDF	edge linking, VLSI, real-time image processing
26	G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim	Yield Optimization by Design Centering and Worst-Case Distance Analysis.	ICCD	1999	DBLP DOI BibTeX RDF	worst-case distance, design centering, optimization, VLSI design, parametric yield
26	Isidoro Urriza, José Ignacio Artigas, José I. García-Nicolás, Luis Angel Barragan, Denis Navarro	VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform.	DATE	1998	DBLP DOI BibTeX RDF	DWT, VLSI architectures, Medical Image compression
26	Kazuyuki Ozaki, Hidenori Sekiguchi, Shinichi Wakana, Yoshiro Goto, Yasutoshi Umehara, Jun Matsumoto	Novel Optical Probing System for Quarter-micron VLSI Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Internal analysis, Prober, Electro-optic Sampling, Scanning Force Microscope, waveform, DC voltage, VLSI Circuits
26	Kyosun Kim, Ramesh Karri, Miodrag Potkonjak	Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems.	ICCAD	1997	DBLP DOI BibTeX RDF	micro-preemption, multi-task VLSI system synthesis, context switch overhead, preemption latency
26	Raghu Sastry, N. Ranganathan, Ramesh C. Jain	VLSI Architectures for High-Speed Range Estimation.	IEEE Trans. Pattern Anal. Mach. Intell.	1995	DBLP DOI BibTeX RDF	very large scale integration (VLSI) implementation, image processing, hardware algorithm, systolic algorithm, special purpose architecture, intensity gradient, Range estimation
26	Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou	Pipelined Memory Shared Buffer for VLSI Switches.	SIGCOMM	1995	DBLP DOI BibTeX RDF	gigabit VLSI switch buffer, multiport buffer, pipelined memory, crossbar switch, shared buffering, input queueing
26	Gloria Kissin	Upper and Lower Bounds on Switching Energy in VLSI.	J. ACM	1991	DBLP DOI BibTeX RDF	1-switchable functions, AND function, CID VLSI circuit, OR functions, USM, circuit scheme, compare functions, parity function, switching energy, uniswitch, energy-efficient, embedding, energy consumption, layout, average-case analysis, addition, upper and lower bounds
26	Michael Formann, Frank Wagner 0001	The VLSI layout in various embedding models.	WG	1990	DBLP DOI BibTeX RDF	embedding models, Manhattan model, knock-knee model, routing, VLSI, NP-completeness, layout
26	Mark H. Nodine, Daniel P. Lopresti, Jeffrey Scott Vitter	I/O Overhead and Parallel VLSI Architectures for Lattice Computations.	ICCI	1990	DBLP DOI BibTeX RDF	Input/output complexity, lattice computations, cellular automata, VLSI architectures, pebbling
26	Michael Deering, Stephanie Winner, Bic Schediwy, Chris Duffy, Neil Hunt	The triangle processor and normal vector shader: a VLSI system for high performance graphics.	SIGGRAPH	1988	DBLP DOI BibTeX RDF	graphics VLSI, hardware lighting models, real-time image display, triangle processor, interpolation, shading
26	Evanthia Papadopoulou	The Hausdorff Voronoi Diagram of Point Clusters in the Plane.	Algorithmica	2004	DBLP DOI BibTeX RDF	VLSI yield prediction, VLSI Critical Area, Via-blocks, Voronoi diagram, Hausdorff distance, Plane sweep, Manufacturing defects
26	Mourad Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, André Tissot	A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology.	CAMP	2000	DBLP DOI BibTeX RDF	pattern recognition architecture, VLSI physical integration, VLSI characteristics, pattern recognition, specification, design methodology, system architecture, system-on-a-chip, hardware/software codesign, heterogeneous architecture
26	Ming Z. Zhang, Hau T. Ngo, Adam R. Livingston, Vijayan K. Asari	An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels.	ISVLSI	2005	DBLP DOI BibTeX RDF	2-D convolution, symmetric kernel, pipelined architecture, systolic architecture
26	Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama	Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure.	ISVLSI	2004	DBLP DOI BibTeX RDF
26	Harpreet S. Narula, John G. Harris	Integrated VLSI Potentiostat for Cyclic Voltammetry in Electrolytic Reactions.	ISVLSI	2004	DBLP DOI BibTeX RDF
26	Shang Xue, Bengt Oelmann	Efficient VLSI Implementation of a VLC Decoder for Universal Variable Length Code.	ISVLSI	2003	DBLP DOI BibTeX RDF
26	Xin He, Afshin Abdollahi	Cost aware fault tolerant logic synthesis in presence of soft errors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	soft error rate, reliability, linear programming
26	Mingjing Chen, Alex Orailoglu	Deflecting crosstalk by routing reconsideration through refined signal correlation estimation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	signal correlation, routing, crosstalk
26	Xu Zhang, Xiaohong Jiang 0001, Susumu Horiguchi	A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	H-Tree, X Architecture, performance evluation, variant X-Tree, clock distribution network
26	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	Energy Efficient VLSI Architecture for Linear Turbo Equalizer.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	iterative equalizer, SISO, turbo, architecture, low-power, iterative decoder
26	A. Benjamin Premkumar, A. S. Madhukumar	An Efficient VLSI Architecture for the Computation of 1-D Discrete Wavelet Transform.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	life time cycle, convolution sum, direct form structures, wavelet transform, filter banks
26	Gang Xu, Sridhar Rajagopal, Joseph R. Cavallaro, Behnaam Aazhang	VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	multistage detector, CDMA, fixed-point, multiuser detection, interference cancellation, real-time implementation
26	Chien-Yu Chen 0001, Zhong-Lan Yang, Tu-Chih Wang, Liang-Gee Chen	A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	wavelet, JPEG 2000, DSP architecture
26	Jaehee You, Sang Uk Lee	High Throughput, Scalable VLSI Architecture for Block Matching Motion Estimation.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
26	Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen	Analog VLSI for robot path planning.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
26	Subir Bandyopadhyay, Graham A. Jullien, Abhijit Sengupta	A fast VLSI systolic array for large modulus residue addition.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
26	Aleksandra Pavasovic, Andreas G. Andreou, Charles R. Westgate	Characterization of subthreshold MOS mismatch in transistors for VLSI systems.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
26	Olaf J. Joeressen, Martin Vaupel, Heinrich Meyr	High-speed VLSI architectures for soft-output viterbi decoding.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
26	Paul M. Chau, Scott R. Powell	Power dissipation of VLSI array processing systems.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
26	Mary Jane Irwin, Robert Michael Owens	A case for digit serial VLSI signal processors.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
26	Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.	ISVLSI	2004	DBLP DOI BibTeX RDF	CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
26	George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis	Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	single-chip ATM switch, VLSI router, pipelined queue management, credit-based flow control
26	Chie Dou, Ming-Der Shieh	A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management.	ICCD	1996	DBLP DOI BibTeX RDF	Shared Buffer ATM Switch, VLSI, Fuzzy Control, Buffer Management, CAM
25	N. Sudha	Design of a Cellular Architecture for Fast Computation of the Skeleton.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	cellular architecture, VLSI, skeleton, binary image
25	Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi	Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	adaptive decoding, MAP algorithm, VLSI implementation, turbo codes
25	Yeong-Kang Lai, Liang-Gee Chen, Tsung-Han Tsai 0001, Po-Cheng Wu	A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation.	ICIP (2)	1997	DBLP DOI BibTeX RDF	flexible high-throughput VLSI architecture, 2D data-reuse, full-search motion estimation, data-interlacing architecture, one-dimensional processing element array, data-interlacing shift-register arrays, external memory accesses, pin counts, search ranges, pixel rates, VLSI, block sizes, full-search block-matching algorithm
25	Cheng-Wen Wu	On energy efficiency of VLSI testing.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test efficiency models, CMOS power consumption model, high testability, high power dissipation, high-power testing, transition activity factor, fabricated chip, testing energy, VLSI, energy efficiency, fault coverage, design optimization, VLSI testing, testing time, test efficiency, testing power
25	Nur A. Touba, Edward J. McCluskey	Test point insertion based on path tracing.	VTS	1996	DBLP DOI BibTeX RDF	probabilistic techniques, primary inputs, insertion methods, VLSI, VLSI, fault diagnosis, logic testing, logic testing, probability, built-in self test, timing, integrated circuit testing, BIST, automatic testing, fault coverage, test point insertion, path tracing, circuit-under-test
25	Jonathan T.-Y. Chang, Edward J. McCluskey	Quantitative analysis of very-low-voltage testing.	VTS	1996	DBLP DOI BibTeX RDF	very-low-voltage testing, static CMOS chips, supply voltage, rated conditions, early-life failures, test conditions, test speed, VLSI, VLSI, integrated circuit testing, CMOS integrated circuits, failure analysis, quantitative analysis, threshold voltage, integrated circuit noise
25	Michel Renovell, P. Huc, Yves Bertrand	Bridging fault coverage improvement by power supply control.	VTS	1996	DBLP DOI BibTeX RDF	bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
25	Valery A. Vardanian	On completely robust path delay fault testable realization of logic functions.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions
25	Hirendu Vaishnav, Massoud Pedram	Delay optimal partitioning targeting low power VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	clustering, VLSI, partitioning, logic CAD, circuit CAD, integrated logic circuits, power dissipation, VLSI circuits, logic partitioning, delay optimal
25	Yu Fang, Alexander Albicki	Efficient testability enhancement for combinational circuit.	ICCD	1995	DBLP DOI BibTeX RDF	testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
25	X. Cai, Keith Nabors, Jacob K. White 0001	Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics.	ARVLSI	1995	DBLP DOI BibTeX RDF	piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures
25	Charles E. Stroud, T. Raju Damarla	Improving the efficiency of error identification via signature analysis.	VTS	1995	DBLP DOI BibTeX RDF	error identification, single bit errors, input polynomial, least common multiple, diagnostic aliasing, multiple bit errors, nonprimitive polynomials, VLSI, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, BIST, signature analysis, characteristic polynomial
25	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
25	Rajesh Nair, Dong Sam Ha	VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flip-flops, synchronous sequential circuits, benchmark circuits
25	Mahsa Vahidi, Alex Orailoglu	Testability metrics for synthesis of self-testable designs and effective test plans.	VTS	1995	DBLP DOI BibTeX RDF	testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs
25	Michel Renovell, P. Huc, Yves Bertrand	The concept of resistance interval: a new parametric model for realistic resistive bridging fault.	VTS	1995	DBLP DOI BibTeX RDF	electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior
25	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
25	Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin	Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	area time trade-offs, micro-grain VLSI array architectures, massively parallel control-flow architectures, associative memory architecture, Mux-based SIMD architecture, systolic MIMD/MISD computation, data-flow requirements, performance evaluation, performance, VLSI, parallel architectures, FFT, matrix multiplication, RAMs
25	Hussein M. Alnuweiri	Optimal VLSI Networks for Multidimensional Transforms.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	optimal VLSI networks, multidimensional transforms, AT/sup 2/-optimal networks, mapping large K-shuffle networks, index-rotation operations, regular layouts, VLSI, fast Fourier transforms, discrete Fourier transform, circuit analysis computing, minimisation of switching nets
25	Jean Duprat, Jean-Michel Muller	The CORDIC Algorithm: New Results for Fast VLSI Implementation.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	sign functions, fast VLSI implementation, signed-digit implementation, carry-save representation, branching CORDIC method, constant normalization factor, online delay, cosine functions, VLSI, signal processing, digital arithmetic, CORDIC algorithm
25	Yuval Tamir, Hsin-Chou Chi	Symmetric Crossbar Arbiters for VLSI Communication Switches.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	VLSI communication switches, symmetric crossbar arbiters, multistage interconnectionnetwork, switch arbitration policy, worst-case latency, circuitsimulation, performance evaluation, VLSI, circuit analysis computing, network simulations, critical path, multiprocessorinterconnection networks, system clock
25	Krishna P. Belkhale, Prithviraj Banerjee	Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	reconfiguration strategies, VLSI processor arrays, Diogenes approach, rectangular arrays, VLSI, fault tolerant computing, trees, trees (mathematics), circuit layout CAD, complete binary tree
25	John Y. Sayah, Charles R. Kime	Test Scheduling in High Performance VLSI System Implementations.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	high performance VLSI system, parallel test execution, organization level, test parallelism, schedulability criteria, suboptimum heuristic-based algorithms, VLSI, built-in self-test, built-in self test, time, integrated circuit testing, design for testability, automatic testing, space, heuristic programming, test scheduling, inherent parallelism
25	Trevor G. Clarkson, Denise Gorse, John G. Taylor, C. K. Ng	Learning Probabilistic RAM Nets Using VLSI Structures.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	synaptic noise, global rewards, global penalties, local penalties, RAM nets, VLSI structures, learning probabilistic RAMs, local reinforcement rules, local rewards, serial updating, VLSI, neural nets, backpropagation, backpropagation, weights, content-addressable storage, stochastic search, learning rule
25	Hussein M. Alnuweiri, Viktor K. Prasanna	Optimal VLSI Sorting with Reduced Number of Processors.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	optimal VLSI sorting, parallel sorting time, sequential complexity, two-dimensional mesh array, trees organization, pyramid computer, computational complexity, VLSI, parallel architecture, parallel architectures, sorting, algorithm complexity
25	Bruno Codenotti, Roberto Tamassia	A Network Flow Approach to the Reconfiguration of VLSI Arrays.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	network flow approach, VLSI arrays, faulty cells, network flow model, functional cells, fault-free array, Manhattan model, VLSI, reconfiguration, systolic arrays, fault location
25	Giuseppe Alia, Enrico Martinelli	A VLSI Modulo m Multiplier.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	modulo m multiplier, residue multiplier, computational complexity, VLSI, VLSI, digital arithmetic, modular multiplications
25	Hon Fung Li, David K. Probst	Optimal VLSI Dictionary Machines Without Compress Instructions.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	optimal VLSI dictionary machines, logarithmic network, design objectives, single-cycle operability, logarithmic network, VLSI, database management systems, trees (mathematics), special purpose computers, linear network, query trees
25	Vwani P. Roychowdhury, Jehoshua Bruck, Thomas Kailath	Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	reconfiguring processor arrays, flexible interconnection structure, array grid model, single-track switches, single-track model, parallel processing, VLSI, VLSI, fault tolerant computing, reconfiguration, polynomial time algorithm, faulty processors, WSI
25	Charles C. Wang, Dingyi Pei	A VLSI DEsign for Computing Exponentiations in GF(2^m) and Its Application to Generate Pseudorandom Number Sequences.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	computing exponentiations, pseudorandom number sequences, VLSI, finite fields, logic CAD, VLSI design, random number generation, multiplying circuits
25	Yuval Tamir, Marc Tremblay	High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fault-tolerant VLSI systems, micro rollback, hardware mechanism, VLSI, fault tolerant computing, error detection, concurrent error detection
25	Peter J. Varman, I. V. Ramakrishnan	Optimal Matrix Multiplication on Fault-Tolerant VLSI Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	optimal matrix multiplication, fault-tolerant VLSI arrays, optimal-time algorithm, 2-D systolic algorithm, simulation, VLSI, fault tolerant computing, reconfigurability, testability, clock cycle
25	Gurindar S. Sohi	Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	cache memory organization, high performance VLSI processors, tolerance of defects faults, linear RAMs, trace-driven simulation analysis, storage management chips, VLSI, yield, fault location, buffer storage, performance degradation, random-access storage, integrated memory circuits
25	Mingshien Wang, Michal Cutler, Stephen Y. H. Su	Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	distributed defects, VLSI/WSI mesh array processors, two-level redundancy, parallel rectangular, operation reliability, clustered defects, complexity, parallel processing, VLSI, fault tolerant computing, reconfiguration, processing elements, optimization technique, combinatorial analysis, manufacturing yield
25	Maheswara R. Samatham, Dhiraj K. Pradhan	The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	de Bruijn multiprocessor network, versatile parallel processing, N-node linear array, N-node ring, one-step shuffle-exchange network, tight lower bound, parallel processing, VLSI, VLSI, fault tolerant computing, multiprocessor interconnection networks, binary trees, sorting network, layout area
25	Hee Yong Youn, Adit D. Singh	On Implementing Large Binary Tree Architectures in VLSI and WSI.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	large binary tree architectures, maximum edge length, H-tree layouts, VLSI, VLSI, layout, trees (mathematics), circuit layout CAD, processing elements, propagation delay, fault-tolerant designs, WSI, two-dimensional array
25	Alan A. Bertossi, Maurizio A. Bonuccelli	A Gracefully Degradable VLSI System for Linear Programming.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	gracefully degradable, fault-tolerant VLSI system, linear programming problems, interconnection pattern, cousin nodes, ternary tree, faulty processing elements, computational complexity, VLSI, fault tolerant computing, linear programming, multiple faults, complete binary tree, simplex algorithm
25	David K. Probst, Hon Fung Li	Abstract Specification of Synchronous Data Types for VLSI and Proving the Correctness of Systolic Network Implementations.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	correctness proving, abstract specification, synchronous data types, systolic network implementations, Parnas trace method, VLSI, VLSI, data structures, data flow, control flow, cellular arrays, software modules
25	Marina C. Chen	The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	highly parallel algorithms synthesis, long multiplication algorithm, binary numbers, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multipliers, Crystal
25	Gary L. Craig, Charles R. Kime, Kewal K. Saluja	Test Scheduling and Control for VLSI Built-In Self-Test.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	test resource sharing, suboptimum algorithms, equal length test, unequal length test, scheduling, VLSI, VLSI, built-in self-test, integrated circuit testing, BIST, automatic testing, hierarchical model, test scheduling, algorithm performance
25	In-Shek Hsu, Trieu-Kien Truong, Leslie J. Deutsch, Irving S. Reed	A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	dual-basis multiplier, Massey-Omura normal basis multiplier, Scott-Tavares-Peppard standard basis multiplier, NMOS technology, VLSI, VLSI architecture, multiplying circuits, finite field multipliers, field effect integrated circuits
25	Adit D. Singh	Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	area efficient fault tolerance scheme, large area VLSI processor arrays, interstitial sites, operational spares, area efficient layouts, chip area utilization, interstitial redundancy, PE survival probabilities, VLSI, fault tolerant computing, reconfiguration, redundancy, polynomial time algorithm, cellular arrays, switching network, performance degradation, wafer scale integration, circuit layout
25	David B. Shu, Ching-Chung Li, J. F. Mancuso, Yung-Nien Sun	A Line Extraction Method for Automated SEM Inspection of VLSI Resist.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	line extraction method, automated SEM inspection, VLSI resist, precision digital edge-line-detection method, edge contours, submicrometer width, integrated circuit fabrication, computer vision, VLSI, transforms, integrated circuit testing, computerised picture processing, automatic testing, Hough transform, inspection, circuit analysis computing, scanning electron microscopy, scanning electron microscopy
25	Arun K. Somani, Vinod K. Agarwal	An Efficient Unsorted VLSI Dictionary Machine.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	Binary tree machines, search machines, systolic systems, unsorted data structures, pipelining, priority queues, VLSI algorithms, VLSI complexity, dictionary machines
25	Thomas Ottmann, Arnold L. Rosenberg, Larry J. Stockmeyer	A Dictionary Machine (for VLSI).	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Algorithms for VLSI, dictionary search, pipelining, systolic array, search tree, VLSI complexity
25		2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zuopu Zhou, Leming Jiao, Zijie Zheng, Xiaolin Wang, Dong Zhang, Kai Ni, Xiao Gong	First Study of the Charge Trapping Aggravation Induced by Anti-Ferroelectric Switching in the MFIS Stack.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang	3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang	A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li	A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Mitsuya Fukazawa, Tetsuo Matsui	A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori	Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Wen-Chieh Chen, S.-H. Chen, Anabela Veloso, Kateryna Serbulova, Geert Hellings, Guido Groeseneken	Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sundeep Javvaji, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Bert Oude-Essink, Koen Beijens, Kofi A. A. Makinwa, Lucien J. Breems	A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sunghyun Yoon, Sung-In Hong, Daehyun Kim, Garam Choi, Young Mo Kim, Kyunghoon Min, Seiyon Kim, Myung-Hee Na, Seonyong Cha	QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Tuur Van Daele, Filip Tavernier	A Fully Integrated 230 VRMS-to-12 VDC AC-DC Converter Achieving 9 mW/mm2.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Mario Sako, T. Nakajima, Fumihiro Kono, T. Nakano, Masaki Fujiu, Junji Musha, Dai Nakamura, Naoaki Kanagawa, Y. Shimizu, Kosuke Yanagidaira, Tetsuaki Utsumi, T. Kawano, Yoshikazu Hosomura, Hiroki Yabe, M. Kano, Hiroshi Sugawara, A. H. Sravan, K. Hayashi, Toshiyuki Kouchi, Y. Watanabe	A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang	A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De	A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Seongil Yeo, Uyong Hyeon, Mingyeong Kim, Jusung Kim, Kunhee Cho	A 19.8W/29.6W Hybrid Step-Up/Down DC-DC Converter with 97.2% Peak Efficiency for 1-Cell/2-Cell Battery Charger Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jiheon Park, Daeyun Kim, Hoyong Lee, Seung-Chul Shin, Myoungoh Ki, Bumsik Chung, Myunghan Bae, Myeonggyun Kye, Jonghan Ahn, Inho Song, Sunhwa Lee, Jaeil An, Il-Pyeong Hwang, Taemin An, Young-Gu Jin, Youngchan Kim, Youngsun Oh, Juhyun Ko, Haechang Lee 0002, Joonseo Yim	An Indirect Time-of-Flight CMOS Image Sensor Achieving Sub-ms Motion Lagging and 60fps Depth Image from On-chip ISP.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Dongqi Zheng, Adam Charnas, Jian-Yu Lin, Jackson Anderson, Dana Weinstein, Peide D. Ye	Ultrathin Atomic-Layer-Deposited In2O3 Radio-Frequency Transistors with Record High fT of 36 GHz and BEOL Compatibility.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jung-Won Han, S. H. Park, M. Y. Jeong, K. S. Lee, K. N. Kim, H. J. Kim, J. C. Shin, S. M. Park, S. H. Shin, S. W. Park, J. H. Lee, S. H. Kim, B. C. Kim, M. H. Jung, I. Y. Yoon, H. Kim, S. U. Jang, K. J. Park, Y. K. Kim, I. G. Kim, J. H. Oh, S. Y. Han, B. S. Kim, B. J. Kuh, J. M. Park	Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sunghwan Kim, Geun-Myeong Kim, Seong-Nam Kim, Saetbyeol Ahn, Yoon-Suk Kim, Inkook Jang, Kyoung-Woo Lee, Dae Sin Kim	Structural Reliability and Performance Analysis of Backside PDN.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura	Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Tathagata Srimani, Andrew C. Yu, Robert M. Radway, Dennis Rich, Mark Nelson, S. Wong, Denis Murphy, Samuel Fuller, Gage Hills, Subhasish Mitra, Max M. Shulaker	Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF