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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 24872 publication records. Showing 24872 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
24 | Wonjae Lee, Seongjoo Lee, Jaeseok Kim |
An Efficient Demosaiced Image Enhancement Method for a Low Cost Single-Chip CMOS Image Sensor. |
PSIVT |
2006 |
DBLP DOI BibTeX RDF |
Single-chip CMOS image sensor, image signal processor, image enhancement, demosaicing |
24 | Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini |
A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
multiple-valued clock, CMOS, flip-flops, multiple-valued logic |
24 | Conrado Rossi, Pablo Aguirre |
Ultra-low power CMOS cells for temperature sensors. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
micropower, CMOS, voltage reference, temperature sensor, current reference |
24 | Leonardo Barboni, Rafaella Fiorelli |
Design and power optimization of CMOS RF blocks operating in the moderate inversion region. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
amplifier design, radio frequency integrated circuits, CMOS integrated circuits, power optimization |
24 | Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia |
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
resistor biasing, low power, wireless, CMOS, low voltage, voltage controlled oscillator (VCO), phase noise |
24 | Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi |
Predictions of CMOS compatible on-chip optical interconnect. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
CMOS compatible, on-chip, optical interconnect, trends |
24 | Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi |
Noise-tolerant high fan-in dynamic CMOS circuit design. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits |
24 | Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas |
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
ECDL, CMOS, adder, digital circuits |
24 | José Vieira do Vale Neto |
Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
LC-tank, ASIC, CMOS, VCO, radio frequency |
24 | Adam O. Lee, Robert J. Weber |
Design of a 5-Gb/s PRBS generator in 0.18µm CMOS process. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
PRBS generator, high-speed buffer, CMOS, current mode logic |
24 | Shaolei Quan, Chin-Long Wey |
A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
CMOS, inductance, RF, LNA |
24 | Maryam Shojaei Baghini, Madhav P. Desai |
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
CMOS latches, Technology Scaling, Metastability |
24 | James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan |
Characterization of CMOS Defects using Transient Signal Analysis. |
DFT |
1998 |
DBLP DOI BibTeX RDF |
transient signal analysis, CMOS defect characterization, defect diagnosis, failure analysis |
24 | Chuan-Yu Wang, Kaushik Roy 0001 |
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
CMOS Digital Circuits, Reliability, Power Estimation |
24 | Rosa Rodríguez-Montañés, Joan Figueras |
Bridges in sequential CMOS circuits: current-voltage signatur. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
sequential CMOS circuits, current-voltage signature, I/sub DDQ/-V/sub DD/ signature, control loop nodes, fault diagnosis, fault diagnosis, temperature dependence, bridging defects |
24 | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana |
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults |
24 | Hideki Fukuda |
Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation. |
ISMVL |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti |
High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi |
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Neil Bergmann |
Generalised CMOS-a technology independent CMOS IC design style. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
23 | Dhiren M. Parmar, Monalisa Sarma, Debasis Samanta |
A Novel Approach to Domino Circuit Synthesis. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar |
Asynchronous gate-diffusion-input (GDI) circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Geun Rae Cho, Tom Chen 0001 |
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Eric Y. Chou, A. J. Budrys, Kit M. Cham |
Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Kevin Ryan, Sansiri Tanachutiwat, Wei Wang 0003 |
3D CMOL Crossnet for Neuromorphic Network Applications. |
NanoNet |
2008 |
DBLP DOI BibTeX RDF |
CMOS-Nano Hybrid System, CMOL, Crossnet, Neuromorphic Network, 3D IC |
22 | Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab |
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current |
22 | Mohammad H. Rahimi, Deborah Estrin, Rick Baer, Henry Uyeno, Jay Warrior |
Cyclops, image sensing and interpretation in wireless networks. |
SenSys |
2004 |
DBLP DOI BibTeX RDF |
cyclops, CMOS imager |
22 | Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar |
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Stephan Henzler, Siegmar Koeppe |
Design and Application of Power Optimized High-Speed CMOS Frequency Dividers. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Ajay Taparia, Thayamkulangara R. Viswanathan |
Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Alexander Fish, Orly Yadid-Pecht |
Low-power "Smart" CMOS image sensors. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Clara Isabel Luján-Martínez, Antonio Jesús Torralba Silgado, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio J. López-Martín |
A -72 dB @ 2 MHz IM3 CMOS tunable pseudo-differential transconductor. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Jon Alfredsson, Snorre Aunet |
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Ahmet Öncü, B. B. M. Wasanthamala Badalawa, Tong Wang 0018, Minoru Fujishima |
22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Chen Dong 0003, Deming Chen, Sansiri Tanachutiwat, Wei Wang 0003 |
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Kenneth K. O, Changhua Cao, Eunyoung Seok, Swaminathan Sankaran |
CMOS Millimeter-Wave Signal Sources and Detectors. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Sorin P. Voinigescu, Sean T. Nicolson, Mehdi Khanpour, Keith K. W. Tang, Kenneth H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, George V. Eleftheriades, Peter Schvan, Ming-Ta Yang |
CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Terence Tam, Graham A. Jullien, Orly Yadid-Pecht |
A CMOS Contact Imager for Cell Detection in Bio-Sensing Applications. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Nadine Gergel-Hackett, Garrett S. Rose, Peter C. Paliwoda, Christina A. Hacker, Curt A. Richter |
On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
hybrid circuits, molecular electronics |
22 | Wei Zhang 0012, Li Shang, Niraj K. Jha |
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Preetham Lakshmikanthan, Adrian Nunez |
A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Suat U. Ay |
Spectral response improvement of CMOS APS pixel through lateral collection. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | K. Praveen Jayakar Thomas, Ram Singh Rana, Yong Lian 0001 |
A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu |
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Variable Input Delay CMOS Logic for Low Power Design. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff |
Soft Delay Error Effects in CMOS Combinational Circuits. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
Soft delay, single event upsets (SEUs), soft error rate (SER), soft errors |
22 | Hiroshi Iwai |
CMOS Scaling for sub-90 nm to sub-10 nm. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ming-Dou Ker, Chia-Sheng Tsai |
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Honglin Wu, Amir Gourgy, Ted H. Szymanski |
An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks. |
LCN |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Alex Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim |
An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang |
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji |
Technology mapping for high-performance static CMOS and pass transistor logic designs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Edgar F. M. Albuquerque, Manuel M. Silva |
Evaluation of substrate noise in CMOS and low-noise logic cells. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | K. Joseph Hass, Jack Venbrux, Prakash Bhatia |
Logic Design Considerations for 0.5-Volt CMOS. |
ARVLSI |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang |
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl |
A minimum total power methodology for projecting limits on CMOS GSI. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
22 | K. Wayne Current |
Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
quaternary, memory, circuit, latch |
22 | Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl |
CMOS system-on-a-chip voltage scaling beyond 50nm. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Maitham Shams, Mohamed I. Elmasry |
Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Reid R. Harrison |
Floating gate current mirror for gain correction in CMOS translinear circuits. |
ISCAS (2) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Kerry S. Lowe, P. Glenn Gulak |
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen |
Efficient timing analysis for CMOS circuits considering data dependent delays. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Jonathan T.-Y. Chang, Edward J. McCluskey |
Detecting resistive shorts for CMOS domino circuits. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Niraj K. Jha |
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Niraj K. Jha, Qiao Tong |
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
22 | F. Joel Ferguson, John Paul Shen |
A CMOS fault extractor for inductive fault analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
21 | |
Compact variability modeling to the rescue. |
IEEE Des. Test Comput. |
2010 |
DBLP DOI BibTeX RDF |
compact variability modeling, nanometer CMOS technology, CMOS technology, design and test |
21 | Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi |
Cyclic greedy generation method for limited number of IDDQ tests. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
cyclic greedy generation method, undetected faults, ISCAS85Y circuits, short circuit faults, fault diagnosis, integrated circuit testing, iterative methods, iterative method, CMOS integrated circuits, IDDQ tests, test patterns, CMOS IC, electric current measurement, cyclic, random patterns |
21 | Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita |
A high-speed IDDQ sensor implementation. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
circuit feedback, high-speed IDDQ sensor implementation, submicron CMOS process, feedback scheme, floppy-disk controller IDDQ test, current sensor, built-in sensor, 0.35 micron, 50 MHz, integrated circuit testing, CMOS digital integrated circuits, BICS, electric current measurement, electric sensing devices |
21 | William C. Athas |
Practical considerations of clock-powered logic. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
ER-CMOS, adiabatic charging, clock-powered logic, energy-recovery CMOS, supply-voltage scaling, microprocessors |
21 | Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang |
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams |
21 | Antoni Ferré, Joan Figueras |
On estimating bounds of the quiescent current for IDDQ testin. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
quiescent current bounds, sensing circuitry design, VLSI, logic testing, integrated circuit testing, ATPG, automatic testing, CMOS integrated circuits, leakage currents, I/sub DDQ/ testing, CMOS ICs, hierarchical approach |
21 | Bapiraju Vinnakota |
Monitoring power dissipation for fault detection. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
power monitoring, CMOS IC testing, VLSI, monitoring, integrated circuit testing, fault detection, fault location, CMOS integrated circuits, power dissipation, frequency-domain analysis, frequency domain analysis, test vectors |
21 | Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis |
An asynchronous totally self-checking two-rail code error indicator. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults |
21 | Steffen Müller |
A new programmable VLSI architecture for histogram and statistics computation in different windows. |
ICIP |
1995 |
DBLP DOI BibTeX RDF |
programmable VLSI architecture, histogram computation, grey-scale histogram, image preprocessing methods, inhomogeneous illumination elimination, simple increment operations, histogrammer, window handling, arithmetic unit configuration, memory configuration, equalisation, simulation, image segmentation, VLSI, segmentation, data compression, data compression, statistics, image enhancement, image enhancement, texture analysis, image texture, digital signal processing chips, CMOS technology, binary images, CMOS digital integrated circuits, co-occurrence-matrix, statistics computation |
21 | Michel Renovell, P. Huc, Yves Bertrand |
Serial transistor network modeling for bridging fault simulation. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
serial transistor network modeling, voting model, biased voting model, relative transistor strength, SPICE pre-simulation, fault simulation procedure, CMOS logic, fault diagnosis, logic testing, integrated circuit testing, digital simulation, circuit analysis computing, CMOS logic circuits, SPICE, integrated circuit modelling, bridging fault simulation |
21 | Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck |
Deterministic test generation for non-classical faults on the gate level. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST |
21 | Irith Pomeranz, Sudhakar M. Reddy |
Static compaction for two-pattern test sets. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults |
21 | Hiroaki Ueda, Kozo Kinoshita |
Low power design and its testability. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability |
21 | Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita |
Transistor leakage fault location with ZDDQ measurement. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution |
21 | Wilbert H. F. J. Körver |
A universal formalization of the effects of threshold voltages for discrete switch-level circuit models. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits |
21 | Nestoras Tzartzanis, William C. Athas |
Design and analysis of a low-power energy-recovery adder. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation |
21 | Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel |
Cyclic stress tests for full scan circuits. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits |
21 | Samy Makar, Edward J. McCluskey |
Checking experiments to test latches. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults |
21 | Peter Lidén, Peter Dahlgren |
Switch-level modeling of transistor-level stuck-at faults. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling |
21 | Javier Argüelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho |
Iddt testing of continuous-time filters. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
continuous time filters, continuous-time filters, design-for-test methodology, dynamic supply current consumption, dynamic current, partitioning methodology, test reliability, built-in self test, integrated circuit testing, design for testability, automatic testing, CMOS, automatic test equipment, built-in current sensor, CMOS analogue integrated circuits |
21 | Víctor H. Champac, Joan Figueras |
Testability of floating gate defects in sequential circuits. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing |
21 | Michael J. Schulte, Earl E. Swartzlander Jr. |
Hardware Designs for Exactly Rounded Elemantary Functions. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
Chebyshev approximation, summing circuits, exactly rounded elementary functions, multi-operand adder, Chebyshev series approximation, single-precision floating point numbers, chip area, 1.0-micron CMOS technology, computational delay, exact rounding, argument reduction, computer arithmetic, digital arithmetic, polynomials, CMOS integrated circuits, multiplying circuits, square-root, hardware designs, reciprocal, approximation theory, polynomial approximation, special-purpose hardware, parallel multiplier, 1 micron |
21 | Vitit Kantabutra |
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron |
21 | Stamatis Vassiliadis, James Phillips, Bart Blaner |
Interlock Collapsing ALU's. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement |
21 | Sterling R. Whitaker, Gary K. Maki |
Self Synchronized Asynchronous Sequential Pass Transistor Circuits. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
self synchronisation, asynchronous sequential pass transistor circuits, CMOS VLSI, critical race free state assignments, VLSI, sequential circuits, CMOS integrated circuits, asynchronous sequential logic |
21 | Parthasarathy P. Tirumalai, Jon T. Butler |
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. |
IEEE Trans. Computers |
1991 |
DBLP DOI BibTeX RDF |
minimisation algorithms, multiple-valued programmable logic arrays, sum-of products, MIN operation, random-symmetric functions, constrained implicant sets, charge-coupled device circuits, performance, CMOS, heuristic algorithms, many-valued logics, minimisation, CMOS integrated circuits, backtracking, logic arrays, tree search, multiple-valued functions, charge-coupled device |
21 | David R. Smith, Jing C. Lin |
The Tree-Match Chip. |
IEEE Trans. Computers |
1991 |
DBLP DOI BibTeX RDF |
subject stream scan, multiple chip cascading, tree-match chip, chip organization, one-bit-wide stacks, functional language processing, 40-pin standard frame, satellite computers, parallel algorithms, VLSI, circuit layout CAD, CMOS integrated circuits, CMOS technology, shift registers, coprocessor, content-addressed memory, tree-pattern-matching |
21 | Belle W. Y. Wei, Clark D. Thompson |
Area-Time Optimal Adder Design. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
area-time optimal adder design, VLSI parallel adder, component cells, static CMOS, floating-point processor, 66 bit, VLSI, dynamic programming, dynamic programming, logic design, digital arithmetic, adders, CMOS integrated circuits, modular design |
21 | John P. Fishburn |
Clock Skew Optimization. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
synchronous digital system, minimum safety margin, performance, linear programs, optimisation, CMOS, circuit analysis computing, flip-flops, circuit simulation, CMOS integrated circuits, path delays, clock signal |
21 | Lindsay Kleeman |
The Jitter Model for Metastability and Its Application to Redundant Synchronizers. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
jitter model, redundant synchronizers, circuit noise, CMOS D-type flip-flop, bistable device, simulation, circuit analysis computing, flip-flops, SPICE, CMOS integrated circuits, integrated logic circuits, reliability analysis, metastability, timing model, circuit analysis |
21 | Eric Regener |
A Transition Sequence Generator for RAM Fault Detection. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
transition sequence generator, RAM fault detection, n-bit CMOS memories, test address sequence, ordered pair, next-state generator, integrated circuit testing, logic circuit, CMOS integrated circuits, random-access storage, integrated memory circuits |
20 | Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang 0003 |
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
CMOS/nano, memristor, multi level memories |
20 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
nano-CMOS, power, leakage, SRAM, static noise margin |
20 | Liqiang Wang, Yan Shi, Zukang Lu, Huilong Duan |
Miniaturized CMOS Imaging Module with Real-time DSP Technology for Endoscope and Laryngoscope Applications. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
CMOS imaging module, Blackfin DSP, Minimally invasive instruments, Real-time video processing, Miniature |
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