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Found 12513 publication records. Showing 12509 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
68Paul E. Hasler, Bradley A. Minch, Chris Diorio Adaptive Circuits Using pFET Floating-Gate Devices. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
68Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu Generation of tenacious tests for small gate delay faults in combinational circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
60Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera Statistical modeling of gate-delay variation with consideration of intra-gate variability. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Paul E. Hasler, Paul D. Smith An autozeroing floating-gate amplifier with gain adaptation. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
58Narender Hanchate, Nagarajan Ranganathan Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay
57Hari Ananthan, Kaushik Roy 0001 A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF leakage distribution, multiple-gate, tri-gate, process variations, finFET, double-gate
56Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 Constructing Current-Based Gate Models Based on Existing Timing Library. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
55A. Madan, S. C. Bose, P. J. George, Chandra Shekhar 0001 Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Direct Tunneling, gate leakage current, high-K gate stack, MOSFETs
54Omid Mirmotahari, Yngvar Berg Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF floating-gate (FG), multiple-valued logic (MVL), bidirectional
53Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang Nanoscale CMOS circuit leakage power reduction by double-gate device. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF double-gate device, short-channel effect, leakage power
53Vijay Sundararajan, Keshab K. Parhi Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Gate-resizing, Buffer-redistribution, near-optimal, library-specific, optimal, low-power
53Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang On Designing of 4-Valued Memory with Double-Gate TFT. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
52Shinichi Kato, Minoru Watanabe Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. Search on Bibsonomy SAMOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
51Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee Explicit gate delay model for timing evaluation. Search on Bibsonomy ISPD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF pre-characterize, delay model, explicit
51Shinya Kubota, Minoru Watanabe A nine-context programmable optically reconfigurable gate array with semiconductor lasers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
50Yoko Sakai, Yoriko Mawatari, Kiyonari Yamasaki, Ko-ichiroh Shohda, Akira Suyama Construction of AND Gate for RTRACS with the Capacity of Extension to NAND Gate. Search on Bibsonomy DNA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF molecular computer, logic gate
50Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang A comparison of via-programmable gate array logic cell circuits. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF logic cell, via-programmable gate arrays
49Keijiro Nakamura Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF number of inversions, Gate-minimum network, inverse edge, MOS complex gate, negative function, negative gate
49Puneet Gupta 0001, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma Eyecharts: constructive benchmarking of gate sizing heuristics. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dynamic programming, benchmarking, gate sizing
49Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein Reliable Laser Programmable Gate Array Technology. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA)
47Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester Gate-length biasing for runtime-leakage control. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Mariam Momenzadeh, Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001 Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage
47Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil The G4-FET: a universal and programmable logic gate. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF G4-FET, programmable gate, universal logic gate, full adder
47Minsik Ahn, Chang-Ho Lee, Joy Laskar CMOS High Power SPDT Switch using Multigate Structure. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Missing-gate faults, quantum computing, reversible logic, testable design, universal test set
45Vishal Khandelwal, Ankur Srivastava 0001 Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
45Samir Roy, Biswajit Saha Minority Gate Oriented Logic Design with Quantum-Dot Cellular Automata. Search on Bibsonomy ACRI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Nano-computing, Minority Gate, Quantum-dot Cellular Automata
45Debjit Sinha, Hai Zhou 0001, Chris C. N. Chu Optimal gate sizing for coupling-noise reduction. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF coupling-noise, gate-sizing, lattice theory, fixpoint
45Zbigniew Palmowski, Sabine Schlegel, Onno J. Boxma A Tandem Queue with a Gate Mechanism. Search on Bibsonomy Queueing Syst. Theory Appl. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF gate mechanism, batch customers, access networks, tandem queue, collision resolution
44Ghassan Al Hayek, Chantal Robach On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification
44Udo Mahlstedt, Jürgen Alt, Matthias Heinitz CURRENT: a test generation system for IDDQ testing. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
43Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy 0001 Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram Dominant critical gate identification for power and yield optimization in logic circuits. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF low-vt, process variations, yield
43Rafik S. Guindi, Farid N. Najm Design Techniques for Gate-Leakage Reduction in CMOS Circuits. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Shuo Huang, Omar Wing Gate matrix partitioning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
43Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng Automatic synthesis of gate-level timed circuits with choice. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
42Mao Nakajima, Daisaku Seto, Minoru Watanabe A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
41Feng Liu, Jin He 0003, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang 0002, Mansun Chan Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF double-gate MOSFET, drain current, compact model
41Ming-Hui Wang, Qun Wan, Zhisheng You A gate size estimation algorithm for data association filters. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF data association filter, gate size, optimal estimation
41Fatih Hamzaoglu, Mircea R. Stan Circuit-level techniques to control gate leakage for sub-100nm CMOS. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF low power, MTCMOS, gate leakage, domino circuits
41Tetsuya Uemura, Toshio Baba Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. Search on Bibsonomy ISMVL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF tunnel transistor, multiple-valued T-gate, D-FF, NDR
41L. F. Fuller, C. Kraaijenvanger Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education
40Chi-Shong Wang, Chingwei Yeh Performance-driven technology mapping with MSG partition and selective gate duplication. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF gate duplication, maximal super-gate, super-gate, dynamic programming, partition, matching, logic synthesis, directed acyclic graph, Technology mapping, covering
40Yulius Denny Prabowo, Erick Fernando, Jullend Gate Evaluation of IT Governance with BAI Domain at Senior High School Using Cobit 5. Search on Bibsonomy ICIMTech The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
40Renato Juliano Martins, Emil Marinov, M. Aziz Ben Youssef, Christina Kyrou, Mathilde Joubert, Constance Colmagro, Valentin Gâté, Colette Turbil, Pierre-Marie Coulon, Daniel Turover, Samira Khadir, Massimo Giudici, Charalambos Klitis, Marc Sorel, Patrice Genevet Metasurface-enhanced Light Detection and Ranging Technology. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
40James Gate, Iain A. Stewart The expressibility of fragments of Hybrid Graph Logic on finite digraphs. Search on Bibsonomy J. Appl. Log. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
40Benjamin Lefaudeux, Gwennael Gate, Fawzi Nashashibi Extended occupation grids for non-rigid moving objects tracking. Search on Bibsonomy ITSC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
40James Gate, Iain A. Stewart Frameworks for Logically Classifying Polynomial-Time Optimisation Problems. Search on Bibsonomy CSR The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
40Gwennael Gate, Amaury Breheret, Fawzi Nashashibi Centralized fusion for fast people detection in dense environment. Search on Bibsonomy ICRA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
40Gwennael Gate, Fawzi Nashashibi An approach for robust mapping, detection, tracking and classification in dynamic environments. Search on Bibsonomy ICAR The full citation details ... 2009 DBLP  BibTeX  RDF
40Gwennael Gate, Amaury Breheret, Fawzi Nashashibi Fast Pedestrian Detection in Dense Environment with a Laser Scanner and a Camera. Search on Bibsonomy VTC Spring The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
39Minoru Watanabe, Fuminori Kobayashi A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. Search on Bibsonomy ARC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Minoru Watanabe, Fuminori Kobayashi A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III A novel approach for variation aware power minimization during gate sizing. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Kaushik Roy 0001, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici Double-Gate SOI Devices for Low-Power and High-Performance Applications. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Venkataraman Mahalingam, N. Ranganathan A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Minoru Watanabe, Fuminori Kobayashi An Improved Dynamic Optically Reconfigurable Gate Array. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Minoru Watanabe, Fuminori Kobayashi An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Soroush Abbaspour, Hanif Fatemi, Massoud Pedram VGTA: Variation Aware Gate Timing Analysis. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Jing Huang 0001, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi Design and characterization of an and-or-inverter (AOI) gate for QCA implementation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF defect characterization, test, QCA
39Ashok K. Murugavel, N. Ranganathan Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. Search on Bibsonomy ISMVL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
38Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Hot Carrier Effect, Gate level modeling, Gate level simulation, Circuit reliability simulation, VLSI
38Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell Design of Variable Input Delay Gates for Low Dynamic Power Circuits. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
37Minoru Watanabe, Fuminori Kobayashi A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
36Sheng Wei 0001, Saro Meguerdichian, Miodrag Potkonjak Gate-level characterization: foundations and hardware security applications. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF gate-level characterization, hardware Trojan horse, thermal conditioning, manufacturing variability
36Lei Cheng 0001, Deming Chen, Martin D. F. Wong A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Input vector control, gate replacement, leakage reduction
36Lei Cheng 0001, Liang Deng, Deming Chen, Martin D. F. Wong A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF gate replacement, input vector control, leakage reduction
36Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand Delay Testing Viability of Gate Oxide Short Defects. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF gate oxide short (GOS), VLSI, delay testing, defect
36Lin Yuan, Gang Qu 0001 Enhanced leakage reduction Technique by gate replacement. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF MLV, gate replacement, leakage reduction
36Amit Agarwal 0001, Kaushik Roy 0001 A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF diode, low leakage cache, SRAM, gate leakage
36Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown Efficient techniques for gate leakage estimation. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF pattern-dependent, pattern-independent, estimation, leakage, gate leakage
36Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj Post-route gate sizing for crosstalk noise reduction. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF crosstalk noise repair, gate sizing
36Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fault modeling, physical defects, gate oxide short
36Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru An iterative gate sizing approach with accurate delay evaluation. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay evaluation, linear program, iteration, gate sizing
36Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models
36R. Burgess, C. Wouters PARAGON: a new package for gate matrix layout synthesis. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF cell generation, gate-matrix layout, routing, simulated annealing, optimisation, placement, logic synthesis, physical design
36Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory
36Yun Ye, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001 Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation
36Rafail Lashevsky, K. Takaara, M. Souma The efficiency of neuron-MOS transistors in threshold logic. Search on Bibsonomy Soft Comput. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Neuron MOS-transistors, threshold gate with alterable parameters, threshold logic
36Irith Pomeranz, Sudhakar M. Reddy Functional test generation for delay faults in combinational circuits. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
35Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Michael Walter Payton, Fat Duen Ho A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Himanshu Thapliyal, Nagarajan Ranganathan Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Vishal Khandelwal, Ankur Srivastava 0001 Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Soroush Abbaspour, Hanif Fatemi, Massoud Pedram Parameterized Non-Gaussian Variational Gate Timing Analysis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Debjit Sinha, Hai Zhou 0001 Gate-size optimization under timing constraints for coupling-noise reduction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang Switching-activity driven gate sizing and Vth assignment for low power design. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 Statistical gate delay calculation with crosstalk alignment consideration. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Narender Hanchate, Nagarajan Ranganathan Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34K. Narasimhulu, V. Ramgopal Rao Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Jayashree Sridharan, Tom Chen 0001 Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Himanshu Thapliyal, M. B. Srinivas A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. Search on Bibsonomy ISMVL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Supratik Chakraborty, Rajeev Murgai Complexity Of Minimum-Delay Gate Resizing. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
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