Search results for "SRAMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian	Reducing Embedded SRAM Test Time under Redundancy Constraints.	VTS	2004	DBLP DOI BibTeX RDF	Memory Test Time, Memory Redundancy, Memory testing, March Tests, Embedded SRAMs
82	Baosheng Wang, Yuejian Wu, André Ivanov	Designs for Reducing Test Time of Distributed Small Embedded SRAMs.	DFT	2004	DBLP DOI BibTeX RDF	Distributed Small Embedded SRAMs, Data Retention Fault Test, Response Analysis, Test Time
77	Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov	A retention-aware test power model for embedded SRAM.	ASP-DAC	2005	DBLP DOI BibTeX RDF	data retention fault test, multiple embedded SRAMs, test power modeling, test scheduling
77	John Woodfill, Brian Von Herzen	Real-time stereo vision on the PARTS reconfigurable computer.	FCCM	1997	DBLP DOI BibTeX RDF	powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access
70	Qiang Xu 0001, Baosheng Wang, F. Y. Young	Retention-Aware Test Scheduling for BISTed Embedded SRAMs.	ETS	2006	DBLP DOI BibTeX RDF
57	Jae Chul Cha, Sandeep K. Gupta 0001	Characterization of granularity and redundancy for SRAMs for optimal yield-per-area.	ICCD	2008	DBLP DOI BibTeX RDF
57	Martin Margala	Low Power SRAMs for Battery Operation.	MTDT	1999	DBLP DOI BibTeX RDF
57	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
57	Said Hamdioui, Ad J. van de Goor	An experimental analysis of spot defects in SRAMs: realistic fault models and tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	integrated circuit testing, fault models, fault coverage, SRAMs, functional fault models, SRAM chips, spot defects
51	Kanad Chakraborty, Pinaki Mazumder	Technology and layout-related testing of static random-access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Array layout, cell technology, Gallium Arsenide (GaAs), high electron mobility transistor (HEMT) RAMs, I DD testing, I DDQ testing
44	Tony Tae-Hyoung Kim, Jason Liu 0004, John Keane 0001, Chris H. Kim	Circuit techniques for ultra-low power subthreshold SRAMs.	ISCAS	2008	DBLP DOI BibTeX RDF
44	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	Automatic March Tests Generation for Multi-Port SRAMs.	DELTA	2006	DBLP DOI BibTeX RDF
44	Baosheng Wang, Yuejian Wu, André Ivanov	A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs.	DATE	2005	DBLP DOI BibTeX RDF
44	Xiaopeng Wang, Marco Ottavi, Fabrizio Lombardi	Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.	DFT	2004	DBLP DOI BibTeX RDF	inter-word fault, testing, memory, detection, Coupling fault
44	Baosheng Wang, Josh Yang, André Ivanov	Reducing Test Time of Embedded SRAMs.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded SRAM test, Inductive Fault Analysis, Memory Redundancy, March Test, Test Time
44	Sandra Irobi, Zaid Al-Ars, Said Hamdioui	Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.	ETS	2011	DBLP DOI BibTeX RDF	Parasitic Bit Line coupling, SRAMs, Memory tests
39	Qing K. Zhu	Memory Generation and Power Distribution In SOC.	DSD	2006	DBLP DOI BibTeX RDF
39	Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif	System-Level SRAM Yield Enhancement.	ISQED	2006	DBLP DOI BibTeX RDF
39	Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar	High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach.	VLSI Design	2006	DBLP DOI BibTeX RDF
39	Yi-Chih Chao, Ji-Kun Lin, Jar-Ferr Yang, Bin-Da Liu	A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter.	APCCAS	2006	DBLP DOI BibTeX RDF
39	Rob Dekker, Frans P. M. Beenker, Loek Thijssen	A realistic fault model and test algorithms for static random access memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
38	Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian	SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.	VTS	2005	DBLP DOI BibTeX RDF	Data Retention Faults, Zero-time DRF Testing, Opens, Embedded SRAMs
31	Bing-Wei Huang, Jin-Fu Li 0001	Efficient diagnosis algorithms for drowsy SRAMs.	ISQED	2009	DBLP DOI BibTeX RDF
31	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks	Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.	IEEE Micro	2008	DBLP DOI BibTeX RDF	caches, process variation, variability, dynamic memory
31	Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev	Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.	ISQED	2008	DBLP DOI BibTeX RDF	critical charge, process variation, Soft error, SRAM
31	Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.	ETS	2007	DBLP DOI BibTeX RDF
31	Franz X. Ruckerbauer, Georg Georgakos	Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena.	IOLTS	2007	DBLP DOI BibTeX RDF	NSER, ASER, multi-bit upset, soft errors and radiation, CMOS, SRAM, SEU
31	Tino Heijmen	Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs.	IOLTS	2007	DBLP DOI BibTeX RDF
31	Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.	VTS	2007	DBLP DOI BibTeX RDF
31	Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min	Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs.	VLSI Design	2007	DBLP DOI BibTeX RDF
31	Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene	Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
31	Prassanna Sithambaram, Alberto Macii, Enrico Macii	Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	DBL, DWL, partitioning, embedded, memories, SRAM, application-specific
31	Jader A. De Lima	An active leakage-injection scheme applied to low-voltage SRAMs.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
31	Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura 0001	Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs.	ITC	2002	DBLP DOI BibTeX RDF
31	Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers	Detecting Unique Faults in Multi-port SRAMs.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
31	Khoan Truong	A Simple Built-In Self Test For Dual Ported SRAMs.	MTDT	2000	DBLP DOI BibTeX RDF
31	Samir Naik, Frank Agricola, Wojciech Maly	Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
26	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
26	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
26	Wei Lin 0010, Bin Liu 0001	Pipelined Parallel AC-Based Approach for Multi-String Matching.	ICPADS	2008	DBLP DOI BibTeX RDF
26	Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham	Adaptive SRAM memory for low power and high yield.	ICCD	2008	DBLP DOI BibTeX RDF
26	Jason Meyer, Fatih Kocan	Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Daniel Sánchez 0003, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam	Implementing Signatures for Transactional Memory.	MICRO	2007	DBLP DOI BibTeX RDF
26	Mohammed Sayed, Wael M. Badawy	A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	computational memory, motion estimation, MPEG-4
26	Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura	Efficient memory architecture for JPEG2000 entropy codec.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Mohammed Sayed, Ihab Amer, Wael M. Badawy	Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex	Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules.	DATE	2005	DBLP DOI BibTeX RDF
26	Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
26	Shyue-Kung Lu	A Novel Built-In Self-Repair Approach for Embedded RAMs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	divided word line, fault tolerance, redundancy, low power design, embedded memory
26	Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka	Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	SRAM test, SRAM-based reconfigurable cell, memory tester, marching test
26	Yong Liu 0023, Zhiqiang Gao, Xiangqing He	A Flexible Embedded SRAM Compiler.	DELTA	2002	DBLP DOI BibTeX RDF
26	Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob	Transparent data-memory organizations for digital signal processors.	CASES	2001	DBLP DOI BibTeX RDF
26	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
26	R. Dean Adams, Phil Shephard III	Silicon-on-Insulator Technology Impacts on SRAM Testing.	VTS	2000	DBLP DOI BibTeX RDF	Fault modeling and simulation, Silicon On Insulator (SOI), Memory testing
26	Norman Margolus	An FPGA architecture for DRAM-based systolic computations.	FCCM	1997	DBLP DOI BibTeX RDF
25	Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir	Analytical models for leakage power estimation of memory array structures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	estimation, SRAMs, leakage power
25	Puneet Sawhney, Haroon Rasheed	Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array.	VLSI Design	1995	DBLP DOI BibTeX RDF	static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators
19	Leonardo Heitich Brendler, Hervé Lapuyade, Yann Deval, Frédéric Darracq, Frédéric Fauquet, Ricardo Reis 0001, François Rivet	A Proof-of-Concept of a Multiple-Cell Upsets Detection Method for SRAMs in Space Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
19	Balaji Narasimham, H. Luk, C. Paone, A-R. Montoya, T. Riehle, Mike Smith, Liming Tsau	Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs.	IRPS	2023	DBLP DOI BibTeX RDF
19	Kazusa Takami, Yuibi Gomi, Shin-ichiro Abe, Wang Liao, Seiya Manabe, Tetsuro Matsumoto, Masanori Hashimoto	Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons.	IRPS	2023	DBLP DOI BibTeX RDF
19	Nicholas J. Pieper, Yoni Xiong, Dennis R. Ball, J. Pasternak, Bharat L. Bhuva	Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node.	IRPS	2023	DBLP DOI BibTeX RDF
19	Gaurav Saraswat, Anuj Parashar	Voltage Boosted Schmitt Trigger Sense Amplifier (VBSTSA) With Improved Offset And Reaction Time For High Speed SRAMs.	VLSID	2023	DBLP DOI BibTeX RDF
19	Christina Dilopoulou, Yiorgos Tsiatouhas	BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs.	MOCAST	2023	DBLP DOI BibTeX RDF
19	Ismail Emir Yüksel, Behzad Salami 0001, Oguz Ergin, Osman Sabri Unsal, Adrián Cristal Kestelman	MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
19	Ismail Emir Yüksel, Ataberk Olgun, Behzad Salami 0001, F. Nisa Bostanci, Yahya Can Tugrul, Abdullah Giray Yaglikçi, Nika Mansouri-Ghiasi, Onur Mutlu, Oguz Ergin	TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs.	CoRR	2022	DBLP DOI BibTeX RDF
19	Joshua Hovanes, Yadi Zhong, Ujjwal Guin	Beware of Discarding Used SRAMs: Information is Stored Permanently.	CoRR	2022	DBLP DOI BibTeX RDF
19	Mukesh Kumar Srivastav, Rimjhim, Roshan Mishra, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat	3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS.	ISCAS	2022	DBLP DOI BibTeX RDF
19	Guilherme Cardoso Medeiros, Moritz Fieback, Lizhou Wu, Mottaqiallah Taouil, Letícia Maria Bolzani Poehls, Said Hamdioui	Hard-to-Detect Fault Analysis in FinFET SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
19	Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi	Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
19	Dhruv Patel 0002, Adam Neale, Derek Wright, Manoj Sachdev	Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
19	Shourya Gupta, Benton H. Calhoun	Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
19	Shourya Gupta, Benton H. Calhoun	Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
19	Monica Gupta, Kirti Gupta, Neeta Pandey	Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm.	Microprocess. Microsystems	2021	DBLP DOI BibTeX RDF
19	Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Letícia Maria Bolzani Poehls, Tiago Roberto Balen	Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.	J. Electron. Test.	2021	DBLP DOI BibTeX RDF
19	Mahmood Uddin Mohammed, Athiya Nizam, Liaquat Ali, Masud H. Chowdhury	FinFET based SRAMs in Sub-10nm domain.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
19	Ismail Emir Yüksel, Behzad Salami 0001, Oguz Ergin, Osman Sabri Unsal, Adrián Cristal Kestelman	MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs.	CoRR	2021	DBLP BibTeX RDF
19	Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda	Comparing different solutions for testing resistive defects in low-power SRAMs.	CoRR	2021	DBLP BibTeX RDF
19	Balaji Narasimham, Vikas Chaudhary, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva	Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET.	IRPS	2021	DBLP DOI BibTeX RDF
19	G. Cardoso Medeiros, Moritz Fieback, Anteneh Gebregiorgis, Mottaqiallah Taouil, Leticia Bolzani Poehls, Said Hamdioui	Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs.	ETS	2021	DBLP DOI BibTeX RDF
19	Mukesh Kumar Srivastav, Rimjhim, Govind Soni, Umang Mittal, Rupali Tewari, Riya Yadav, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat	Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.	ICECS	2021	DBLP DOI BibTeX RDF
19	Kailash Prasad, Aditya Biswas, Joycee Mekie	Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs.	ICECS	2021	DBLP DOI BibTeX RDF
19	Jean-Philippe Noel, M. Pezzin, Jean-Frédéric Christmann, Lorenzo Ciampolini, M. Le Coadou, M. Diallo, Florent Lepin, B. Blampey, Simone Bacles-Min, R. Wacquez, Bastien Giraud	A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs.	ESSCIRC	2021	DBLP DOI BibTeX RDF
19	Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Narendra Kumar Pulipati, Joy Chen, Teja Masina	Robust Adaptive Read Scheme for 7nm Configuration SRAMs.	IOLTS	2021	DBLP DOI BibTeX RDF
19	Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda	Comparing different solutions for testing resistive defects in low-power SRAMs.	LATS	2021	DBLP DOI BibTeX RDF
19	Mohammadreza Rezaei, Francisco J. Franco, Juan Carlos Fabero, Hortensia Mecha, Helmut Puchner, Juan Antonio Clemente	Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs.	LATS	2021	DBLP DOI BibTeX RDF
19	Chang Cai, Luchang Ding, Ze He, Jian Yu, Jie Liu, Jiyuan Bai, Gengsheng Chen, Jun Yu 0010	Simulation of SEU Response of Advanced 20 nm FDSOI SRAMs.	ASICON	2021	DBLP DOI BibTeX RDF
19	Vinod Kumar, Ram Murti Rawat	Low Power Swing Restoration Circuit Reduce Threshold Voltages of SRAMs Improve Read and Write Operations.	iSES	2021	DBLP DOI BibTeX RDF
19	G. Cardoso Medeiros, Moritz Fieback, Thiago Santos Copetti, Anteneh Gebregiorgis, Mottaqiallah Taouil, Leticia B. Poehls, Said Hamdioui	Improving the Detection of Undefined State Faults in FinFET SRAMs.	DTIS	2021	DBLP DOI BibTeX RDF
19	Raj Kumar Maity, Sayan Tripathi, Jagannath Samanta, Jaydeb Bhaumik	Lower complexity error location detection block of adjacent error correcting decoder for SRAMs.	IET Comput. Digit. Tech.	2020	DBLP DOI BibTeX RDF
19	Michael A. Turi, José G. Delgado-Frias	Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
19	Thiago Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls	Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects.	J. Electron. Test.	2020	DBLP DOI BibTeX RDF
19	Akhilesh Jaiswal 0001, Amogh Agrawal, Mustafa Fayez Ali, Saima Sharmin, Kaushik Roy 0001	i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
19	Wang Liao, Kojiro Ito, Yukio Mitsuyama, Masanori Hashimoto	Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs.	IRPS	2020	DBLP DOI BibTeX RDF
19	Chang Cai, Tianqi Liu, Jie Liu 0032, Gengsheng Chen, Luchang Ding, Kai Zhao, Bingxu Ning, Mingjie Shen	Large-tilt Heavy Ions Induced SEU in Multiple Radiation Hardened 22 nm FDSOI SRAMs.	IRPS	2020	DBLP DOI BibTeX RDF
19	Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil, Said Hamdioui	A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.	DATE	2020	DBLP DOI BibTeX RDF
19	Jin-Fu Li 0001, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun	Testing of Configurable 8T SRAMs for In-Memory Computing.	ATS	2020	DBLP DOI BibTeX RDF
19	Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet	Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology.	NorCAS	2020	DBLP DOI BibTeX RDF
19	Karim Ali 0004, Fei Li 0015, Sunny Y. H. Lua, Chun-Huat Heng	Energy Efficient Reduced Area Overhead Spin-Orbit Torque Non-Volatile SRAMs.	IECON	2020	DBLP DOI BibTeX RDF
19	Kumar Rahul, Santosh Yachareni	Deterministic Algorithm to generate SEC-DED-DAEC H-Matrix for SRAMs in FPGAs for reliable space applications.	ICCCS	2020	DBLP DOI BibTeX RDF
19	Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Leticia Bolzani Poehls, Tiago R. Balen	Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.	LATS	2020	DBLP DOI BibTeX RDF