Search results for "Combinational"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
83	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
78	Marc D. Riedel, Jehoshua Bruck	The synthesis of cyclic combinational circuits.	DAC	2003	DBLP DOI BibTeX RDF	feedback, logic synthesis, cycles, combinational logic
76	Sukumar Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
72	Yuji Kukimoto, Robert K. Brayton	Timing-safe false path removal for combinational modules.	ICCAD	1999	DBLP DOI BibTeX RDF
70	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
66	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Combinational automatic test pattern generation for acyclic sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
59	Yang Xia, Pranav Ashar	Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture.	VLSI Design	2000	DBLP DOI BibTeX RDF	Combinational Loop, Model Checking, Formal Verification, Temporal Logic, Time Division Multiplexing, Token Ring, Computational Tree Logic, Bus Protocol
58	José Monteiro 0001, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
53	Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas	Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
51	Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu	VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	combinational broadcaster, combinational compactor, fault diagnosis, ATPG, test compression, low-power testing, scan testing
51	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
51	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
50	Gosta Pada Biswas, Idranil Sen Gupta	Generalized modular design of testable m-out-of-n code checker.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable m-out-of-n code checker, combinational logic port, combinational logic cells, unidirectional faults, complementary outputs, VLSI, fault diagnosis, logic testing, cellular automata, combinational circuits, fault location, stuck-at faults, logic arrays, cellular automaton, modular design, iterative array, initial state
46	Nian-chu Zeng, Weidong Li 0005	Research on the Combinational Evaluation of the Market Value of Listed Company.	WKDD	2009	DBLP DOI BibTeX RDF
46	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
46	Sharad Malik	Analysis of cyclic combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
46	Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song	Transforming Cyclic Circuits Into Acyclic Equivalents.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
46	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure
46	Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya	Logical redundancies in irredundant combinational circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	irredundancy, testing, Boolean functions, combinational circuits, stuck-at faults, fanouts
45	Aarti Gupta, Pranav Ashar	Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.	VLSI Design	1998	DBLP DOI BibTeX RDF	ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs)
45	Xiaoming Yu, Yinghua Min	Design of delay-verifiable combinational logic by adding extra inputs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	delay-verifiable combinational logic, delay testability, synthesis, combinational circuits, hardware overhead, temporal behavior
45	Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi	Formal Verification Of Self-Testing Properties Of Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code
45	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
45	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
45	Xunwei Wu, Xiexiong Chen, Jizhong Shen	Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits.	ISMVL	1995	DBLP DOI BibTeX RDF	race-hazard, skip-hazard, multivalued combinational circuits, race hazards, AND/OR expression, skip hazard, multivalued circuits, fast transition, small load capacitor, combinational circuits, multivalued logic circuits, hazards and race conditions, input signals
45	Abdel-Fattah Yousif, Jun Gu	Concurrent automatic test pattern generation algorithm for combinational circuits.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent automatic test pattern generation algorithm, global computations techniques, concurrent search, ISCAS'85, ISCAS'89 benchmarks, computational complexity, logic testing, NP-hard, combinational circuits, combinational circuits, automatic testing
45	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
45	Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy	MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.	VLSI Design	1995	DBLP DOI BibTeX RDF	MUSTC-testing, multi-stage-combinational test, control paths, signal types, module level pre-computed test sets, scheduling, logic testing, integrated circuit testing, combinational circuits, automatic testing, automatic test, register-transfer level, test scheduling, data-paths
45	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
45	Sreejit Chakravarty, Yiming Gong	Voting model based diagnosis of bridging faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure
44	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
44	Mitrajit Chatterjee, Dhiraj K. Pradhan	A novel pattern generator for near-perfect fault-coverage.	VTS	1995	DBLP DOI BibTeX RDF	near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault
40	Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004	IR-drop Reduction Through Combinational Circuit Partitioning.	PATMOS	2006	DBLP DOI BibTeX RDF	Static Timing Analysis, IR-drop, circuit partitioning
40	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Soft Delay Error Effects in CMOS Combinational Circuits.	VTS	2004	DBLP DOI BibTeX RDF	Soft delay, single event upsets (SEUs), soft error rate (SER), soft errors
40	Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal	Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.	VLSI Design	2001	DBLP DOI BibTeX RDF
40	Hideo Fujiwara	A New Class of Sequential Circuits with Combinational Test Generation Complexity.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
40	Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen	Equivalence checking of combinational circuits using Boolean expression diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
40	Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell	An efficient filter-based approach for combinational verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
40	Dimitrios Kagaris, Spyros Tragoudas	A fast algorithm for minimizing FPGA combinational and sequential modules.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	field programmable gate arrays, retiming
40	Vishwani D. Agrawal, Srimat T. Chakradhar	Combinational ATPG theorems for identifying untestable faults in sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
40	Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Retiming and resynthesis: optimizing sequential networks with combinational techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
39	Morteza Fayyazi, Laurent Kirsch	Efficient simulation of oscillatory combinational loops.	DAC	2010	DBLP DOI BibTeX RDF	oscillatory combinational loops, emulation, functional verification
39	Paul Tarau, Brenda Luderman	A Logic Programming Framework for Combinational Circuit Synthesis.	ICLP	2007	DBLP DOI BibTeX RDF	logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis
39	Mukul R. Prasad, Philip Chong, Kurt Keutzer	Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	combinational ATPG, SAT, backtracking, complexity analysis, VLSI circuits
39	João Marques-Silva 0001, Thomas Glass	Combinational Equivalence Checking Using Satisfiability and Recursive Learning.	DATE	1999	DBLP DOI BibTeX RDF	Boolean Satisfiability, Recursive Learning, Combinational Equivalence Checking
39	Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton	Combinational Verification based on High-Level Functional Specifications.	DATE	1998	DBLP DOI BibTeX RDF	Combinational verification, Domain transformations, BDDs
38	Vishwani D. Agrawal, David Lee 0001	Characteristic polynomial method for verification and test of combinational circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational circuit test, randomly selected integers, input variables, integer-valued transform functions, fixed domain, multiple samples, randomly selected real numbers, output logic, logic testing, probability, Boolean functions, Boolean functions, combinational circuits, polynomials, error probability, characteristic polynomial
38	Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu	Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron beam testing, multiple fault diagnosis, sensitized paths, EB testing, TP-1, TP-2, TP-3, TP-4, electron-beam tester, internal lines, VLSI, fault diagnosis, logic testing, combinational circuits, combinational circuits, fault location, fault location, stuck-at faults, diagnostic resolution
38	Yu Fang, Alexander Albicki	Efficient testability enhancement for combinational circuit.	ICCD	1995	DBLP DOI BibTeX RDF	testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
38	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
38	Alessandro Bogliolo, Maurizio Damiani	Synthesis of combinational circuits with special fault-handling capabilitie.	VTS	1995	DBLP DOI BibTeX RDF	combinational circuit synthesis, fault-handling capabilities, internal faults, multilevel logic optimization process, logic testing, redundancy, redundancy, design for testability, logic design, combinational circuits, logic CAD, multivalued logic, circuit optimisation, self-checking circuits, circuit reliability, fault-tolerant circuits
38	S. A. Ali, G. Robert Redinbo	Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	tight lower bounds, internal signal lines, fault diagnosis, logic testing, combinational circuits, combinational circuits, random testing, detection probabilities, single faults
38	Yacoub M. El-Ziq, Stephen Y. H. Su	Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	diagnosable networks, easily testable networks, field-effect transistors, logic design automation, metal-oxide semiconductor, Boolean functions, logic synthesis, testability, combinational logic, combinational networks, statistical data, computer algorithm
38	Klaus Ecker, Dieter Schütt	Computational Work of Combinational Machines.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Boolean matrix, combinational complexity, combinational machine (logic circuit), computational work of processes, transformation of Boolean functions
38	Anastasios Vergis, Carlos Tobon 0002	Testing trees for multiple faults.	VTS	1996	DBLP DOI BibTeX RDF	testing trees, combinational logic cells, tree-structured circuits, VLSI, logic testing, integrated circuit testing, design for testability, logic design, combinational circuits, integrated logic circuits, multiple faults, test set size
38	Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
38	Chen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin	Fast fault simulation for BIST applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	signature computation, BIST applications, combinational fault simulation, BISTSIM, demand-driven logic simulation algorithm, fault propagation methods, bit-array computation, parallel-pattern sequential simulation, speedup ratio, VLSI, VLSI, logic testing, built-in self test, integrated circuit testing, combinational circuits, digital simulation, circuit analysis computing, aliasing, test patterns, MISR
38	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
37	Chuck Monahan, Forrest Brewer	Symbolic execution of data paths.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	combinational switching, data-path model, path constraints, bus hazards, register constraints, control encoding limitations, path-constrained model, DSP microprocessor, switching logic, connection constraints, operand constraints, scheduling, Boolean functions, Boolean functions, logic design, combinational circuits, data flow analysis, processor scheduling, symbolic execution, data flow graphs, digital signal processing chips, constraint handling, combinational logic, dataflow graphs, hazards and race conditions, memory elements
33	Chao-Jung Hsu, Chin-Yu Huang	Reliability analysis using weighted combinational models for web-based software.	WWW	2009	DBLP DOI BibTeX RDF	genetic algorithm., weighted combination, software reliability growth model
33	Carlos Arthur Lang Lisbôa, Luigi Carro	XOR-based Low Cost Checkers for Combinational Logic.	DFT	2008	DBLP DOI BibTeX RDF
33	Rajesh Garg, Charu Nagpal, Sunil P. Khatri	A fast, analytical estimator for the SEU-induced pulse width in combinational designs.	DAC	2008	DBLP DOI BibTeX RDF	single event upset (SEU), model, analysis
33	In-Ho Moon, Per Bjesse, Carl Pixley	A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.	DATE	2007	DBLP DOI BibTeX RDF
33	Zhonghua Li, Hongzhou Tan	A Combinational Clustering Method Based on Artificial Immune System and Support Vector Machine.	KES (1)	2006	DBLP DOI BibTeX RDF
33	André K. Nieuwland, Samir Jasarevic, Goran Jerin	Combinational Logic Soft Error Analysis and Protection.	IOLTS	2006	DBLP DOI BibTeX RDF
33	Nima Honarmand, Ali Afzali-Kusha	Low Power Combinational Multipliers using Data-driven Signal Gating.	APCCAS	2006	DBLP DOI BibTeX RDF
33	Tran Van Dung	On the Stability Semantics of Combinational Programs.	ICTAC	2005	DBLP DOI BibTeX RDF
33	Wai Shing Lau, Gang Li 0016, Kin-Hong Lee, Kwong-Sak Leung, Sin Man Cheang	Multi-logic-Unit Processor: A Combinational Logic Circuit Evaluation Engine for Genetic Parallel Programming.	EuroGP	2005	DBLP DOI BibTeX RDF
33	Carlos A. Coello Coello, Erika Hernández Luna, Arturo Hernández Aguirre	A Comparative Study of Encodings to Design Combinational Logic Circuits Using Particle Swarm Optimization.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
33	Bassam Shaer, Khaled Dib	An Efficient Partitioning Algorithm of Combinational CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF	partitioning, pseudoexhaustive testing
33	Ramesh C. Tekumalla, Premachandran R. Menon	Identification of primitive faults in combinational and sequentialcircuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
33	Hideo Fujiwara	A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity.	VLSI Design	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
33	Yong Je Lim, Mani Soma	Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
33	Luis Entrena-Arrontes, Kwang-Ting Cheng	Combinational and sequential logic optimization by redundancy addition and removal.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
33	Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer	Statistical timing analysis of combinational logic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
33	Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton	On breakable cyclic definitions.	ICCAD	2004	DBLP DOI BibTeX RDF
33	Kip C. Killpack, Eric Mercer, Chris J. Myers	A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
32	Ozgur Sinanoglu	Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Combinational decompressors, Scan cell partitioning, Test data compression, Scan-based testing
32	Paul Tarau, Brenda Luderman	Revisiting exact combinational circuit synthesis.	SAC	2008	DBLP DOI BibTeX RDF	exact combinational circuit synthesis, logic programming and circuit design, minimal transistor-count circuit synthesis
32	Zhifang Li, Wenjian Luo, Xufa Wang	A Stepwise Dimension Reduction Approach to Evolutionary Design of Relative Large Combinational Logic Circuits.	ICES	2008	DBLP DOI BibTeX RDF	Evolutionary Algorithm, Evolvable Hardware, Combinational Logic Circuits
32	Stefan Disch, Christoph Scholl 0001	Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets.	ASP-DAC	2007	DBLP DOI BibTeX RDF	shared circuit structures, incremental SAT techniques, bounded model checking, combinational equivalence checking
32	Audhild Vaaje	Theorems for Fault Collapsing in Combinational Circuits.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	Boolean function, combinational circuit, monotonic function, fault collapsing
32	Rui Liu, Sanyou Zeng, Lixin Ding, Lishan Kang, Hui Li, Yuping Chen, Yong Liu 0012, Yueping Han	An Efficient Multi-Objective Evolutionary Algorithm for Combinational Circuit Design.	AHS	2006	DBLP DOI BibTeX RDF	Gartesian Genetic Programming, Multiobjective Evolutionary Algorithm, Combinational logic Circuit
32	Nirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar	An Efficient Method to Generate Test Vectors for Combinational Cell Verification.	VLSI Design	2004	DBLP DOI BibTeX RDF	combinational cell verification, Gray-code, vector generation, Euler tour
32	Aiman H. El-Maleh, Yahya E. Osais	Test vector decomposition-based static compaction algorithms for combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Static compaction, class-based clustering, independent fault clustering, test vector decomposition, taxonomy, combinational circuits
32	Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple	Combinational equivalence checking through function transformation.	ICCAD	2002	DBLP DOI BibTeX RDF	combinational verification, equivalence checking
32	Aarti Gupta, Pranav Ashar	Fast Error Diagnosis for Combinational Verification.	VLSI Design	2000	DBLP DOI BibTeX RDF	Satisfiability Checking, Formal Verification, Combinational Circuits, Binary Decision Diagrams, Logic Simulation, Error Diagnosis
32	Irith Pomeranz, Sudhakar M. Reddy	Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	test generation, combinational circuits, stuck-at faults, logic simulation
32	Zhide Zeng, Jihua Chen, Hefeng Cao	Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	finite backtracking test pattern generation, n to 1 tightly coupled integration mode, parallel-pattern, single-fault propagation, ultra large scale combinational circuit (ULSCC
32	Irith Pomeranz, Sudhakar M. Reddy	On Test Compaction Objectives for Combinational and Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements
32	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
32	Liliana Díaz-Olavarrieta, Safwat G. Zaky	A new synthesis technique for multilevel combinational circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF	testing, mappings, synthesis, Combinational
32	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
31	Wei-Yu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
31	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
31	Emil Gizdarski, Hideo Fujiwara	Spirit: satisfiability problem implementation for redundancy identification and test generation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
31	Ellen Sentovich	Quick Conservative Causality Analysis.	ISSS	1997	DBLP DOI BibTeX RDF	quick conservative causality analysis, causality problem, standard logic synthesis techniques, combinational circuits, combinational circuit, conservative algorithm
31	Yiming Gong, Sreejit Chakravarty	Using fault sampling to compute IDDQ diagnostic test set.	VTS	1997	DBLP DOI BibTeX RDF	fault sampling, IDDQ diagnostic test set generation, combinational circuits, combinational circuit, bridging faults
31	Valery A. Vardanian	Exact probabilistic analysis of error detection for parity checkers.	VTS	1997	DBLP DOI BibTeX RDF	circuit under check, multi-output supergate, combinational CUC, restricted observability, restricted detectability, concurrent checker, latency, error detection, combinational circuits, probabilistic analysis, single stuck-at fault, parity checker
31	Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz	On minimizing the number of test points needed to achieve complete robust path delay fault testability.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion