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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 738 occurrences of 250 keywords
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Results
Found 594 publication records. Showing 594 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
88 | Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell |
Functional test generation for path delay faults. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults |
84 | Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen |
Identification of robust untestable path delay faults. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification |
72 | Kwang-Ting Cheng, Hsi-Chuan Chen |
Classification and identification of nonrobust untestable path delay faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
71 | Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar |
Primitive delay faults: identification, testing, and design for testability. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
70 | Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |
Diagnostic of path and gate delay faults in non-scan sequential circuits. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults |
67 | Mukund Sivaraman, Andrzej J. Strojwas |
Diagnosis of parametric path delay faults. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing |
66 | Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal |
Test Generation for Path Delay Faults Using Binary Decision Diagrams. |
IEEE Trans. Computers |
1995 |
DBLP DOI BibTeX RDF |
Boolean algebraic test generation, redundant delay faults, robust delay tests, scan testing of delay faults, binary decision diagrams, delay faults |
66 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests |
66 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
On test coverage of path delay faults. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths |
66 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. |
J. Electron. Test. |
1997 |
DBLP DOI BibTeX RDF |
digital circuit testing, test generation, fault models, delay test, path delay faults |
65 | Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu |
Generation of tenacious tests for small gate delay faults in combinational circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage |
63 | Bo Yao, Irith Pomeranz, Sudhakar M. Reddy |
Deterministic broadside test generation for transition path delay faults. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
broadside test, deterministic test generation, path delay fault, transition fault |
62 | Mukund Sivaraman, Andrzej J. Strojwas |
A diagnosability metric for parametric path delay faults. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set |
60 | Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski |
On computing the sizes of detected delay faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
60 | Irith Pomeranz, Sudhakar M. Reddy |
Vector-Based Functional Fault Models for Delay Faults. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
functional tests, delay faults, path delay faults |
59 | Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu |
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. |
PRDC |
2002 |
DBLP DOI BibTeX RDF |
|
59 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
Fast identification of untestable delay faults using implications. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
|
59 | I-De Huang, Yi-Shing Chang, Sandeep K. Gupta 0001, Sreejit Chakravarty |
An Industrial Case Study of Sticky Path-Delay Faults. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
sticky paths, timing false paths, path reprioritization, delay testing, test quality |
59 | Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
A circuit level fault model for resistive bridges. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
fault models, bridge faults, delay faults |
57 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga |
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
marginal delay, test generation, combinational circuit, gate delay faults |
55 | Irith Pomeranz, Sudhakar M. Reddy |
Test enrichment for path delay faults using multiple sets of target faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
53 | Zhongcheng Li, Yinghua Min, Robert K. Brayton |
A New Low-Cost Method for Identifying Untestable Path Delay Faults. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
non-robustly untestable, Delay testing, path delay fault, implication |
53 | Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik |
A BIST scheme for the detection of path-delay faults. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
53 | Irith Pomeranz, Sudhakar M. Reddy |
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
52 | József Sziray |
Test Calculation for Logic and Delay Faults in Digital Circuits. |
MTV |
2006 |
DBLP DOI BibTeX RDF |
Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic |
52 | Ramesh C. Tekumalla, Premachandran R. Menon |
On Redundant Path Delay Faults in Synchronous Sequential Circuits. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
functional sensitizability, sequential circuits, testability, Path delay faults, redundant faults |
52 | Cecilia Metra, Martin Omaña 0001, Daniele Rossi 0001, José Manuel Cazeaux, T. M. Mak |
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
51 | William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Delay fault coverage, test set size, and performance trade-offs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
51 | Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy |
Fsimac: a fault simulator for asynchronous sequential circuits. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits |
51 | Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz |
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
A Test Generator for Segment Delay Faults. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
51 | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
A Complete Characterization of Path Delay Faults through Stuck-at Faults. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
50 | Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell |
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
BIST, delay faults, look-up table |
48 | Joonhwan Yi, John P. Hayes |
The Coupling Model for Function and Delay Faults. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
test generation, fault modeling, delay faults, functional faults |
48 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi |
False-Path Removal Using Delay Fault Simulation. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal |
47 | Ramesh C. Tekumalla, Scott Davidson 0001 |
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation |
46 | Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz |
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. |
ETS |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
An efficient automatic test generation system for path delay faults in combinational circuits. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests |
45 | Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri |
NEST: a nonenumerative test generation method for path delay faults in combinational circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
44 | Eun Sei Park, M. Ray Mercer |
An efficient delay test generation system for combinational logic circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
44 | Eun Sei Park, M. Ray Mercer |
An Efficient Delay Test Generation System for Combinational Logic Circuits. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
44 | Andrzej Krasniewski |
Self-Testing of FPGA Delay Faults in the System Environment. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
FPGA, BIST, random testing, delay faults |
44 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
43 | Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges |
Statistical estimation of delay fault detectabilities and fault grading. |
J. Electron. Test. |
1996 |
DBLP DOI BibTeX RDF |
transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns |
42 | Stephan Eggersglüß, Rolf Drechsler |
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Boolean Encodings, ATPG, SAT, Path Delay Faults |
42 | Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas |
Low power ATPG for path delay faults. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults, PODEM |
42 | Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor |
Opens and Delay Faults in CMOS RAM Address Decoders. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
address decoder delay faults, addressing methods, BIST, DFT, Memory testing, open defects |
42 | Ankan K. Pramanick, Sudhakar M. Reddy |
Efficient multiple path propagating tests for delay faults. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
delay testing, path delay faults, robust tests, test efficiency |
41 | Irith Pomeranz, Sudhakar M. Reddy |
Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch |
An advanced diagnostic method for delay faults in combinational faulty circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
simulation, diagnosis, delay fault, critical path tracing |
41 | Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li 0001, D. M. H. Walker, Weiping Shi |
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing |
41 | Kyriakos Christou, Maria K. Michael, Spyros Tragoudas |
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults |
41 | Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis |
Concurrent Delay Testing in Totally Self-Checking Systems. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators |
41 | Kaamran Raahemifar, Majid Ahmadi |
A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
40 | Feng Shi 0010, Yiorgos Makris |
Testing delay faults in asynchronous handshake circuits. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
test generation, asynchronous circuits, delay faults, handshake circuits |
40 | Irith Pomeranz, Sudhakar M. Reddy |
A Postprocessing Procedure of Test Enrichment for Path Delay Faults. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu |
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
39 | Mukund Sivaraman, Andrzej J. Strojwas |
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
fabrication process, coverage, delay testing, delay fault, path sensitization |
39 | Pei-Fu Shen, Huawei Li 0001, Yongjun Xu, Xiaowei Li 0001 |
Non-robust Test Generation for Crosstalk-Induced Delay Faults. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal |
Path Delay Testing: Variable-Clock Versus Rated-Clock. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test |
38 | Andrzej Krasniewski |
Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda |
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
SBST, path-delay faults, microprocessor test |
38 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas |
Low power test generation for path delay faults using stability functions. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults |
38 | Cheng-Wen Wu, Chih-Yuang Su |
A Probabilistic Model for Path Delay Faults. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Weiwei Mao, Michael D. Ciletti |
Reducing correlation to improve coverage of delay faults in scan-path design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
37 | Thomas W. Williams, Stephen K. Sunter |
How Should Fault Coverage Be Defined? |
VTS |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng |
Off-Line Testing of Delay Faults in NoC Interconnects. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski |
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Andrzej Krasniewski |
Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Maria K. Michael, Spyros Tragoudas |
ATPG tools for delay faults at the functional level. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing |
37 | Andrzej Krasniewski |
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Weiwei Mao, Michael D. Ciletti |
A Variable Observation Time Method for Testing Delay Faults. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
35 | Jais Abraham, Uday Goel, Arun Kumar |
Multi-Cycle Sensitizable Transition Delay Faults. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Karl Fuchs, Michael Pabst, Torsten Rössel |
RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
35 | Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara |
Single-control testability of RTL data paths for BIST. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test |
35 | Mukund Sivaraman, Andrzej J. Strojwas |
Primitive path delay faults: identification and their use in timinganalysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz |
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Ramesh C. Tekumalla, Premachandran R. Menon |
Test generation for primitive path delay faults in combinational circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
Sensitizing cubes, static sensitizability, primitive faults, test generation |
34 | Ananta K. Majhi, Vishwani D. Agrawal |
Tutorial: Delay Fault Models and Coverage. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test |
34 | Andrzej Krasniewski, Leszek B. Wronski |
Coverage of Delay Faults: When 13% and 99% Mean the Same. |
EDCC |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
33 | Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve |
Accurate microarchitecture-level fault modeling for studying hardware faults. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Mukund Sivaraman, Andrzej J. Strojwas |
Timing analysis based on primitive path delay fault identification. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing |
33 | Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell |
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Emil Gizdarski |
Detection of Delay Faults in Memory Address Decoders. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
Built-In Self-Test, delay testing, stuck-open faults, RAM testing |
33 | Pankaj Pant, Abhijit Chatterjee |
Efficient diagnosis of path delay faults in digital logic circuits. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Ramesh C. Tekumalla, Premachandran R. Menon |
Identifying Redundant Path Delay Faults in Sequential Circuits. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
33 | Daniel Brand, Vijay S. Iyengar |
Identification of redundant delay faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
33 | Irith Pomeranz, Sudhakar M. Reddy |
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
33 | Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger |
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin |
Partial scan delay fault testing of asynchronous circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
robust path delay fault testing, asynchronous circuits, delay faults, sequential testing |
32 | Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
Path delay test compaction with process variation tolerance. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
process variation, delay testing, path delay fault, test compaction |
32 | Vivekananda M. Vedula, Jacob A. Abraham |
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
Enhancement of Clock Delay Faults Testing. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Clock line, Test Generation, Delay faults |
31 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel |
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
BIST, delay faults, scan design |
31 | Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas |
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. |
DFT |
1998 |
DBLP DOI BibTeX RDF |
robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays |
31 | Irith Pomeranz, Sudhakar M. Reddy |
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
Lower bound on test set size, pipelining, multipliers, path delay faults, resynthesis |
31 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
Segment delay faults: a new fault model. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects |
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