Search results for "I DDQ"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
155	Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal	Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
143	Manoj Sachdev	Reducing the CMOS RAM test complexity withIDDQ and voltage testing.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	fault model, faults, defects, March test, I DDQ testing
129	Steven D. McEuen	Reliability benefits of IDDQ.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	reliability, I DDQ, Gate oxide shorts
128	Antoni Ferré, Joan Figueras	On estimating bounds of the quiescent current for IDDQ testin.	VTS	1996	DBLP DOI BibTeX RDF	quiescent current bounds, sensing circuitry design, VLSI, logic testing, integrated circuit testing, ATPG, automatic testing, CMOS integrated circuits, leakage currents, I/sub DDQ/ testing, CMOS ICs, hierarchical approach
128	Roger Perry	IDDQ testing in CMOS digital ASICs.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	early life failures, I DDQ current, stuck-at fault, bridging fault, Automatic test program generation
112	Oleg Semenov, Arman Vassighi, Manoj Sachdev	Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	MOSFET leakage, reliability, quality, CMOS integrated circuits, I DDQ testing
109	Peter C. Maxwell, Robert C. Aitken	IDDQ testing as a component of a test suite: The need for several fault coverage metrics.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	quality, fault coverage, scan, functional testing, Current testing, physical defects
101	Claude Thibeault	On Faster IDDQ Measurements.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	ASA-I DDQ, I DDQ
100	Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana	Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults
98	Antoni Ferré, Joan Figueras	LEAP: An Accurate Defect-Free IDDQ Estimator.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	leakage current, I DDQ
97	Sreejit Chakravarty, Paul J. Thadikaran	Algorithms to select IDDQ measurement points to detect bridging faults.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	bridging faults, test selection, I DDQ test
95	Erik Chmelar, Shahin Toutounchi	FPGA Bridging Fault Detection and Location via Differential I{DDQ}.	VTS	2004	DBLP DOI BibTeX RDF
95	Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada	Test Time Reduction for I DDQ Testing by Arranging Test Vectors.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
81	Claude Thibeault	Replacing IDDQ Testing: With Variance Reduction.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	(Delta) I DDQ testing, HBTP, test, variance reduction
81	Rosa Rodríguez-Montañés, Joan Figueras	Bridges in sequential CMOS circuits: current-voltage signatur.	VTS	1997	DBLP DOI BibTeX RDF	sequential CMOS circuits, current-voltage signature, I/sub DDQ/-V/sub DD/ signature, control loop nodes, fault diagnosis, fault diagnosis, temperature dependence, bridging defects
81	Manoj Sachdev	SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	junction leakage current, diagnostics, deep sub-micron, I DDQ testing, subthreshold leakage current
81	Weiwei Mao, Ravi K. Gulati	Quietest: A methodology for selecting IDDQ test vectors.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	weak faults, I DDQ testing, Leakage faults
80	Sagar S. Sabade, D. M. H. Walker	On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set.	VTS	2004	DBLP DOI BibTeX RDF
80	Josep Rius Vázquez, José Pineda de Gyvez	Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs.	VTS	2004	DBLP DOI BibTeX RDF
67	Masaru Sanada	Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	various current, visual abnormalities, fault diagnosis, manufacturing, I DDQ
67	Walter W. Weber, Adit D. Singh	Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	open faults, BIST, fault coverage, built in current sensor, BICS, I DDQ
67	Jerry M. Soden, Charles F. Hawkins, Ravi K. Gulati, Weiwei Mao	IDDQ testing: A review.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	IC quality, fault models, defects, Current testing, CMOS IC, I DDQ
66	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of IDDQ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
66	Tzuhao Chen, Ibrahim N. Hajj	GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment.	ICCAD	1997	DBLP DOI BibTeX RDF	GOLDENGATE, digital VLSI circuits, electrical-level simulation, event-driven technique, logic/I/sub DDQ/ testing, logic testing, sequential circuits, combinational circuits, bridging fault simulator
62	Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins, Vivek De	Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
51	Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic	Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	I DDT, quiescent signal analysis, test, power grids, I DDQ
50	Stephan P. Athan, David L. Landis, Sami A. Al-Arian	A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs.	VTS	1996	DBLP DOI BibTeX RDF	deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
50	Anne E. Gattiker, Wojciech Maly	Current signatures [VLSI circuit testing].	VTS	1996	DBLP DOI BibTeX RDF	VLSI circuit testing, current signature, passive defects, active defects, VLSI, integrated circuit testing, CMOS integrated circuits, I/sub DDQ/ testing
50	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
50	Jaume A. Segura 0001, Miquel Roca 0001, Diego Mateo, Antonio Rubio 0001	An approach to dynamic power consumption current testing of CMOS ICs.	VTS	1995	DBLP DOI BibTeX RDF	dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current
50	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
50	Walter W. Weber, Adit D. Singh	An experimental evaluation of the differential BICS for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	differential BICS, CMOS test chips, inter-layer shorts, intra-layer shorts, fault diagnosis, integrated circuit testing, fault coverage, CMOS integrated circuits, opens, built-in current sensor, IC testing, I/sub DDQ/ testing, electric current measurement, electric sensing devices
50	Josep Rius 0001, Joan Figueras	Detecting IDDQ defective CMOS circuits by depowering.	VTS	1995	DBLP DOI BibTeX RDF	I/sub DDQ/ defective CMOS circuits, depowering, fault detection capabilities, quiescent state, logic valves, discharge current, power supply line disconnection, logic testing, integrated circuit testing, fault location, CMOS logic circuits, capacitance
50	Josep Rius 0001, Joan Figueras	Proportional BIC sensor for current testing.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Built-in integrated sensor, CMOS lateral BJT, gate controlled BJT, I DDQ measure, current test
35	Claude Thibeault	On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Delta ${rm I}_{DDQ}$, probabilistic signatures, diagnosis, Integrated circuits, bridging faults, multiple faults
35	Márta Rencz, Vladimír Székely, S. Török, Kholdoun Torki, Bernard Courtois	IDDQ Testing of Submicron CMOS - by Cooling?	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	submicron, cooling, I DDQ testing
35	Michael G. McNamer, H. Troy Nagle	ITA: An algorithm for IDDQ testability analysis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	integrated circuit testing, testability analysis, I DDQ testing, leakage faults
35	Josep Rius 0001, Joan Figueras	Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	I DDQ testability, Built-in Current Sensors, current testing
35	Jian Liu, Rafic Z. Makki	Power supply current detectability of SRAM defects.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect
35	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
35	Marcello Dalpasso, Michele Favalli, Piero Olivo	Test pattern generation for IDDQ: increasing test quality.	VTS	1995	DBLP DOI BibTeX RDF	ATPG strategy, quiescent power supply current monitoring, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, CMOS logic circuits, I/sub DDQ/ testing
35	Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira 0001	Test preparation for high coverage of physical defects in CMOS digital ICs.	VTS	1995	DBLP DOI BibTeX RDF	high defect coverage, CMOS digital ICs, pseudo realistic faults generation, test quality assessment, tabloid, iceTgen, I/sub DDQ/ test generation, test preparation, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, CMOS digital integrated circuits, physical defects
35	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
35	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
35	Sreejit Chakravarty, Minsheng Liu	Algorithms for IDDQ measurement based diagnosis of bridging faults.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Bridging faults, diagnosis algorithm, I DDQ testing
35	Robert C. Aitken	Diagnosis of leakage faults with IDDQ.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	leakage fault model, Fault diagnosis, I DDQ testing
33	Yicheng Liu, Junwei Zhang	Misalignment tolerance improvement and high efficiency design for wireless power transfer system based on DDQ-DD coil.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
33	Can Wang, Hui Zhang, Yi Tang	DDQ: Collaborating Against Common DNS-Resolver-based Trackers.	ICCT	2023	DBLP DOI BibTeX RDF
33	Xue Mei, Guangyang Zhang, Chongyan Gu, Yao Wang	DDQ-APUF: A Highly Reliable Arbiter PUF Using Delay Difference Quantization.	AsianHOST	2023	DBLP DOI BibTeX RDF
33	Kicheon Kim	Distributed Digitized Delay Queueing (DDQ) for Large Scale QoS Router.	PDPTA	2004	DBLP BibTeX RDF
33	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo	CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
33	Samir Naik, Frank Agricola, Wojciech Maly	Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
33	Ronald R. Fritzemeier, Jerry M. Soden, R. Keith Treece, Charles F. Hawkins	Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets.	ITC	1990	DBLP DOI BibTeX RDF
31	Sagar S. Sabade, D. M. H. Walker	Estimation of fault-free leakage current using wafer-level spatial information.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
31	Won Woo Ro, Jean-Luc Gaudiot	Design and Effectiveness of Small-Sized Decoupled Dispatch Queues.	Euro-Par	2006	DBLP DOI BibTeX RDF
31	Claude Thibeault	On New Current Signatures and Adaptive Test Technique Combination.	VTS	2004	DBLP DOI BibTeX RDF
20	Chun-Hung Chen, Jacob A. Abraham	Generation and evaluation of current and logic tests for switch-level sequential circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	logic tests, test generation, Current tests, I DDQ
19	Bapiraju Vinnakota	Monitoring Power Dissipation for Fault Detection.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	I DDt test, power dissipation test, spectral analysis, I DDQ test
19	Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee	Built-in current sensor designs based on the bulk-driven technique.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement
19	Kanad Chakraborty, Pinaki Mazumder	Technology and layout-related testing of static random-access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Array layout, cell technology, Gallium Arsenide (GaAs), high electron mobility transistor (HEMT) RAMs, I DD testing, I DDQ testing
16	A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky	A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.	IOLTS	2004	DBLP DOI BibTeX RDF
16	Najwa Aaraj, Anis Nazer, Ali Chehab, Ayman I. Kayssi	Transient Current Testing of Dynamic CMOS Circuits.	DFT	2004	DBLP DOI BibTeX RDF
16	Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy 0001	IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
16	Michele Favalli, Cecilia Metra	Bridging Faults in Pipelined Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	fault modeling, bridging faults, CMOS circuits, pipelined circuits
16	Eugeni Isern 0001, Miquel Roca 0001, Jaume Segura 0001	Analyzing the Need for ATPG Targeting GOS Defects.	VTS	1999	DBLP DOI BibTeX RDF
16	Jien-Chung Lo	Highly Reliable Systems with Differential Built-In Current Sensors.	DFT	1998	DBLP DOI BibTeX RDF	reliability, concurrent error detection, supplying current monitoring
16	Yu-Yau Guo, Jien-Chung Lo	Challenges of Built-In Current Sensor Designs.	DFT	1998	DBLP DOI BibTeX RDF	voltage regulator, built-in current sensor, Current testing, decoupling capacitor
16	Peter C. Maxwell, Jeff Rearick	Estimation of defect-free IDDQ in submicron circuits using switch level simulation.	ITC	1998	DBLP DOI BibTeX RDF
16	Vinay Dabholkar, Sreejit Chakravarty	Computing Stress Tests for Gate Oxide Shorts.	VLSI Design	1998	DBLP DOI BibTeX RDF	burn-in, stress tests, gate oxide shorts
16	Sreejit Chakravarty	On the capability of delay tests to detect bridges and opens.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	defective IC, faulty dynamic logic behavior, transition tests, simulation, integrated circuit testing, delay tests, bridges, opens, at-speed testing, path delay tests
16	Claude Thibeault	A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures.	VTS	1997	DBLP DOI BibTeX RDF	IC diagnosis, probabilistic differential quiescent current signature, noise source, embedded logic, robustness, maximum likelihood estimation, maximum likelihood estimation, IDDQ testing, subthreshold leakage current
16	Shyang-Tai Su, Rafic Z. Makki, H. Troy Nagle	Transient power supply current monitoring - A new test method for CMOS VLSI circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	Design for current-testability, drain/source opens, floating gates, shorts, transient power supply current
16	Yiming Gong, Sreejit Chakravarty	On adaptive diagnostic test generation.	ICCAD	1995	DBLP DOI BibTeX RDF
16	Jaume A. Segura 0001, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio	Quiescent current analysis and experimentation of defective CMOS circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Bridging failures, floating gate opens, intentionally designed defective circuits defects, current testing, defect modeling, gate oxide shorts
16	Wojciech Maly, Marek J. Patyra	Design of ICs applying built-in current testing.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	BIC-testing, Built-in testing, current testing