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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 259 occurrences of 107 keywords
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Results
Found 75 publication records. Showing 75 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
155 | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1245-1255, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
143 | Manoj Sachdev |
Reducing the CMOS RAM test complexity withIDDQ and voltage testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 191-202, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fault model, faults, defects, March test, I DDQ testing |
129 | Steven D. McEuen |
Reliability benefits of IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 327-335, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
reliability, I DDQ, Gate oxide shorts |
128 | Antoni Ferré, Joan Figueras |
On estimating bounds of the quiescent current for IDDQ testin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 106-111, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
quiescent current bounds, sensing circuitry design, VLSI, logic testing, integrated circuit testing, ATPG, automatic testing, CMOS integrated circuits, leakage currents, I/sub DDQ/ testing, CMOS ICs, hierarchical approach |
128 | Roger Perry |
IDDQ testing in CMOS digital ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 317-325, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
early life failures, I DDQ current, stuck-at fault, bridging fault, Automatic test program generation |
112 | Oleg Semenov, Arman Vassighi, Manoj Sachdev |
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 341-352, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
MOSFET leakage, reliability, quality, CMOS integrated circuits, I DDQ testing |
109 | Peter C. Maxwell, Robert C. Aitken |
IDDQ testing as a component of a test suite: The need for several fault coverage metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 305-316, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
quality, fault coverage, scan, functional testing, Current testing, physical defects |
101 | Claude Thibeault |
On Faster IDDQ Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(6), pp. 625-635, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ASA-I DDQ, I DDQ |
100 | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana |
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 545-546, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults |
98 | Antoni Ferré, Joan Figueras |
LEAP: An Accurate Defect-Free IDDQ Estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 267-274, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
leakage current, I DDQ |
97 | Sreejit Chakravarty, Paul J. Thadikaran |
Algorithms to select IDDQ measurement points to detect bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 275-285, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bridging faults, test selection, I DDQ test |
95 | Erik Chmelar, Shahin Toutounchi |
FPGA Bridging Fault Detection and Location via Differential I{DDQ}. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 109-116, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
95 | Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada |
Test Time Reduction for I DDQ Testing by Arranging Test Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 423-428, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
81 | Claude Thibeault |
Replacing IDDQ Testing: With Variance Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 325-340, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
(Delta) I DDQ testing, HBTP, test, variance reduction |
81 | Rosa Rodríguez-Montañés, Joan Figueras |
Bridges in sequential CMOS circuits: current-voltage signatur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 68-73, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
sequential CMOS circuits, current-voltage signature, I/sub DDQ/-V/sub DD/ signature, control loop nodes, fault diagnosis, fault diagnosis, temperature dependence, bridging defects |
81 | Manoj Sachdev |
SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(2), pp. 203-214, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
junction leakage current, diagnostics, deep sub-micron, I DDQ testing, subthreshold leakage current |
81 | Weiwei Mao, Ravi K. Gulati |
Quietest: A methodology for selecting IDDQ test vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 349-357, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
weak faults, I DDQ testing, Leakage faults |
80 | Sagar S. Sabade, D. M. H. Walker |
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 65-72, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
80 | Josep Rius Vázquez, José Pineda de Gyvez |
Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 53-58, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
67 | Masaru Sanada |
Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 275-281, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
various current, visual abnormalities, fault diagnosis, manufacturing, I DDQ |
67 | Walter W. Weber, Adit D. Singh |
Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(2), pp. 147-156, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
open faults, BIST, fault coverage, built in current sensor, BICS, I DDQ |
67 | Jerry M. Soden, Charles F. Hawkins, Ravi K. Gulati, Weiwei Mao |
IDDQ testing: A review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 291-303, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
IC quality, fault models, defects, Current testing, CMOS IC, I DDQ |
66 | Toshiyuki Maeda, Kozo Kinoshita |
Memory reduction of IDDQ test compaction for internal and external bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 350-355, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction |
66 | Tzuhao Chen, Ibrahim N. Hajj |
GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 555-561, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
GOLDENGATE, digital VLSI circuits, electrical-level simulation, event-driven technique, logic/I/sub DDQ/ testing, logic testing, sequential circuits, combinational circuits, bridging fault simulator |
62 | Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins, Vivek De |
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 863-870, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
51 | Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic |
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(6), pp. 611-623, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
I DDT, quiescent signal analysis, test, power grids, I DDQ |
50 | Stephan P. Athan, David L. Landis, Sami A. Al-Arian |
A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 118-123, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices |
50 | Anne E. Gattiker, Wojciech Maly |
Current signatures [VLSI circuit testing]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 112-117, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VLSI circuit testing, current signature, passive defects, active defects, VLSI, integrated circuit testing, CMOS integrated circuits, I/sub DDQ/ testing |
50 | Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel |
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 456-462, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm |
50 | Jaume A. Segura 0001, Miquel Roca 0001, Diego Mateo, Antonio Rubio 0001 |
An approach to dynamic power consumption current testing of CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 95-100, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current |
50 | Udo Mahlstedt, Jürgen Alt, Matthias Heinitz |
CURRENT: a test generation system for IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 317-323, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults |
50 | Walter W. Weber, Adit D. Singh |
An experimental evaluation of the differential BICS for IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 472-485, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
differential BICS, CMOS test chips, inter-layer shorts, intra-layer shorts, fault diagnosis, integrated circuit testing, fault coverage, CMOS integrated circuits, opens, built-in current sensor, IC testing, I/sub DDQ/ testing, electric current measurement, electric sensing devices |
50 | Josep Rius 0001, Joan Figueras |
Detecting IDDQ defective CMOS circuits by depowering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 324-329, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
I/sub DDQ/ defective CMOS circuits, depowering, fault detection capabilities, quiescent state, logic valves, discharge current, power supply line disconnection, logic testing, integrated circuit testing, fault location, CMOS logic circuits, capacitance |
50 | Josep Rius 0001, Joan Figueras |
Proportional BIC sensor for current testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 387-396, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Built-in integrated sensor, CMOS lateral BJT, gate controlled BJT, I DDQ measure, current test |
35 | Claude Thibeault |
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 575-587, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Delta ${rm I}_{DDQ}$, probabilistic signatures, diagnosis, Integrated circuits, bridging faults, multiple faults |
35 | Márta Rencz, Vladimír Székely, S. Török, Kholdoun Torki, Bernard Courtois |
IDDQ Testing of Submicron CMOS - by Cooling? ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 453-461, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
submicron, cooling, I DDQ testing |
35 | Michael G. McNamer, H. Troy Nagle |
ITA: An algorithm for IDDQ testability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 287-298, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
integrated circuit testing, testability analysis, I DDQ testing, leakage faults |
35 | Josep Rius 0001, Joan Figueras |
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(3), pp. 295-310, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
I DDQ testability, Built-in Current Sensors, current testing |
35 | Jian Liu, Rafic Z. Makki |
Power supply current detectability of SRAM defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 367-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect |
35 | Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita |
Transistor leakage fault location with ZDDQ measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 51-57, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution |
35 | Marcello Dalpasso, Michele Favalli, Piero Olivo |
Test pattern generation for IDDQ: increasing test quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 304-309, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ATPG strategy, quiescent power supply current monitoring, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, CMOS logic circuits, I/sub DDQ/ testing |
35 | Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Test preparation for high coverage of physical defects in CMOS digital ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 330-337, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high defect coverage, CMOS digital ICs, pseudo realistic faults generation, test quality assessment, tabloid, iceTgen, I/sub DDQ/ test generation, test preparation, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, CMOS digital integrated circuits, physical defects |
35 | Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara |
Compact test generation for bridging faults under IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 310-316, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing |
35 | Víctor H. Champac, Joan Figueras |
Testability of floating gate defects in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 202-207, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing |
35 | Sreejit Chakravarty, Minsheng Liu |
Algorithms for IDDQ measurement based diagnosis of bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 377-385, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Bridging faults, diagnosis algorithm, I DDQ testing |
35 | Robert C. Aitken |
Diagnosis of leakage faults with IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 367-375, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
leakage fault model, Fault diagnosis, I DDQ testing |
33 | Yicheng Liu, Junwei Zhang |
Misalignment tolerance improvement and high efficiency design for wireless power transfer system based on DDQ-DD coil. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 52(1), pp. 111-128, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
33 | Can Wang, Hui Zhang, Yi Tang |
DDQ: Collaborating Against Common DNS-Resolver-based Trackers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCT ![In: 23rd IEEE International Conference on Communication Technology, ICCT 2023, Wuxi, China, October 20-22, 2023, pp. 1325-1329, 2023, IEEE, 979-8-3503-2595-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
33 | Xue Mei, Guangyang Zhang, Chongyan Gu, Yao Wang |
DDQ-APUF: A Highly Reliable Arbiter PUF Using Delay Difference Quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsianHOST ![In: Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2023, Tianjin, China, December 13-15, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-4099-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
33 | Kicheon Kim |
Distributed Digitized Delay Queueing (DDQ) for Large Scale QoS Router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA '04, June 21-24, 2004, Las Vegas, Nevada, USA, Volume 3, pp. 1183-1190, 2004, CSREA Press. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
33 | Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo |
CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 417-422, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Samir Naik, Frank Agricola, Wojciech Maly |
Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(2), pp. 13-23, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
33 | Ronald R. Fritzemeier, Jerry M. Soden, R. Keith Treece, Charles F. Hawkins |
Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 427-435, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
31 | Sagar S. Sabade, D. M. H. Walker |
Estimation of fault-free leakage current using wafer-level spatial information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(1), pp. 91-94, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Won Woo Ro, Jean-Luc Gaudiot |
Design and Effectiveness of Small-Sized Decoupled Dispatch Queues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 485-494, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Claude Thibeault |
On New Current Signatures and Adaptive Test Technique Combination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 59-64, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Chun-Hung Chen, Jacob A. Abraham |
Generation and evaluation of current and logic tests for switch-level sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 359-366, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
logic tests, test generation, Current tests, I DDQ |
19 | Bapiraju Vinnakota |
Monitoring Power Dissipation for Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(2), pp. 173-181, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
I DDt test, power dissipation test, spectral analysis, I DDQ test |
19 | Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee |
Built-in current sensor designs based on the bulk-driven technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 384-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement |
19 | Kanad Chakraborty, Pinaki Mazumder |
Technology and layout-related testing of static random-access memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(4), pp. 347-365, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Array layout, cell technology, Gallium Arsenide (GaAs), high electron mobility transistor (HEMT) RAMs, I DD testing, I DDQ testing |
16 | A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky |
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 52-57, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Najwa Aaraj, Anis Nazer, Ali Chehab, Ayman I. Kayssi |
Transient Current Testing of Dynamic CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 264-271, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy 0001 |
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(2), pp. 24-33, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Michele Favalli, Cecilia Metra |
Bridging Faults in Pipelined Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(6), pp. 617-629, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fault modeling, bridging faults, CMOS circuits, pipelined circuits |
16 | Eugeni Isern 0001, Miquel Roca 0001, Jaume Segura 0001 |
Analyzing the Need for ATPG Targeting GOS Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 420-425, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Jien-Chung Lo |
Highly Reliable Systems with Differential Built-In Current Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 261-269, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reliability, concurrent error detection, supplying current monitoring |
16 | Yu-Yau Guo, Jien-Chung Lo |
Challenges of Built-In Current Sensor Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 192-, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
voltage regulator, built-in current sensor, Current testing, decoupling capacitor |
16 | Peter C. Maxwell, Jeff Rearick |
Estimation of defect-free IDDQ in submicron circuits using switch level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 882-889, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Vinay Dabholkar, Sreejit Chakravarty |
Computing Stress Tests for Gate Oxide Shorts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 378-391, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
burn-in, stress tests, gate oxide shorts |
16 | Sreejit Chakravarty |
On the capability of delay tests to detect bridges and opens. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 314-319, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
defective IC, faulty dynamic logic behavior, transition tests, simulation, integrated circuit testing, delay tests, bridges, opens, at-speed testing, path delay tests |
16 | Claude Thibeault |
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 80-87, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
IC diagnosis, probabilistic differential quiescent current signature, noise source, embedded logic, robustness, maximum likelihood estimation, maximum likelihood estimation, IDDQ testing, subthreshold leakage current |
16 | Shyang-Tai Su, Rafic Z. Makki, H. Troy Nagle |
Transient power supply current monitoring - A new test method for CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 23-43, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Design for current-testability, drain/source opens, floating gates, shorts, transient power supply current |
16 | Yiming Gong, Sreejit Chakravarty |
On adaptive diagnostic test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 181-184, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Jaume A. Segura 0001, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio |
Quiescent current analysis and experimentation of defective CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 337-348, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Bridging failures, floating gate opens, intentionally designed defective circuits defects, current testing, defect modeling, gate oxide shorts |
16 | Wojciech Maly, Marek J. Patyra |
Design of ICs applying built-in current testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 397-406, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
BIC-testing, Built-in testing, current testing |
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