Search results for "gate-delay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
110	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
87	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	Statistical modeling of gate-delay variation with consideration of intra-gate variability.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
64	Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee	Explicit gate delay model for timing evaluation.	ISPD	2003	DBLP DOI BibTeX RDF	pre-characterize, delay model, explicit
55	Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye	A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.	ICCAD	2006	DBLP DOI BibTeX RDF	gate delay model, variability, static timing analysis, statistical timing analysis
54	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Statistical gate delay calculation with crosstalk alignment consideration.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
54	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga	A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	marginal delay, test generation, combinational circuit, gate delay faults
51	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Constructing Current-Based Gate Models Based on Existing Timing Library.	ISQED	2006	DBLP DOI BibTeX RDF
51	Hiran Tennakoon, Carl Sechen	Nonconvex Gate Delay Modeling and Delay Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
49	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
47	Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss	Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.	VLSI Design	1999	DBLP DOI BibTeX RDF
46	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	Diagnostic of path and gate delay faults in non-scan sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
45	Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen	An efficient gate delay model for VLSI design.	ICCD	2007	DBLP DOI BibTeX RDF
45	Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam	An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits.	DAC	1988	DBLP BibTeX RDF
44	Jayashree Sridharan, Tom Chen 0001	Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis.	VLSI Design	2006	DBLP DOI BibTeX RDF
44	Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage	Modeling the "Effective capacitance" for the RC interconnect of CMOS gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
41	Ankan K. Pramanick, Sudhakar M. Reddy	On the fault coverage of gate delay fault detecting tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
41	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	on-chip inductance, shielding effect, propagation delay, interconnect modeling, gate delay
39	Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III	A novel approach for variation aware power minimization during gate sizing.	ISLPED	2006	DBLP DOI BibTeX RDF
39	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VGTA: Variation Aware Gate Timing Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
39	Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo	Test Generation for Multiple-Threshold Gate-Delay Fault Model.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
38	Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera	Statistical gate delay model for Multiple Input Switching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
38	M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor	Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.	ITC	2002	DBLP DOI BibTeX RDF	compact test sets, ATPG, fault coverage, stuck-at faults, test length, Test point insertion, gate-delay faults
37	Jayashree Sridharan, Tom Chen 0001	Modeling multiple input switching of CMOS gates in DSM technology using HDMR.	DATE	2006	DBLP DOI BibTeX RDF
35	Srinivas Devadas, Kurt Keutzer	Addendum to "Synthesis of robust delay-fault testable circuits: Theory".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
34	Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap	Fast Interconnect and Gate Timing Analysis for Performance Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
34	Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen	Efficient timing analysis for CMOS circuits considering data dependent delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
33	Satish K. Yanamanamanda, Jun Li 0066, Janet Meiling Wang	Uncertainty modeling of gate delay considering multiple input switching.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
32	Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala	A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	1-out-of-N code, minimum gate delay, NOR array, NOR-NOR PLA, fault tolerant computing, logic testing, delays, logic design, translator, error detection codes, logic arrays, totally self-checking checker
32	Y. Satish Kumar, Jun Li 0066, Claudio Talarico, Janet Meiling Wang	A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching.	DATE	2005	DBLP DOI BibTeX RDF
32	Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel	Experimental Studies on SAT-Based ATPG for Gate Delay Faults.	ISMVL	2007	DBLP DOI BibTeX RDF
32	Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin	Sensitivity-Based Gate Delay Propagation in Static Timing Analysis.	ISQED	2005	DBLP DOI BibTeX RDF
31	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
30	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Parameterized Non-Gaussian Variational Gate Timing Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
30	Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
30	Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind	Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
29	Soumitra Bose, Vishwani D. Agrawal	Delay Test Quality Evaluation Using Bounded Gate Delays.	VTS	2007	DBLP DOI BibTeX RDF
28	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu	Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
28	Amit Goel, Sarma B. K. Vrudhula	Statistical waveform and current source based standard cell models for accurate timing analysis.	DAC	2008	DBLP DOI BibTeX RDF	statistical waveform models, process variations, timing analysis
28	Yu Cao, Lawrence T. Clark	Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
27	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Asymptotically Scalable Superscalar Processors.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
27	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.	VLSI Design	2003	DBLP DOI BibTeX RDF
25	Aseem Agarwal, Florentin Dartu, David T. Blaauw	Statistical gate delay model considering multiple input switching.	DAC	2004	DBLP DOI BibTeX RDF	performance, Algorithms, reliability
25	Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu	Retiming with Interconnect and Gate Delay.	ICCAD	2003	DBLP DOI BibTeX RDF
25	Frank Poehl, Walter Anheier	Quality Determination for Gate Delay Fault Tests Considering Three-State Elements.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	ATPG, fault modelling, fault simulation
25	Janet Meiling Wang, Jun Li 0066, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla	Modeling the Driver Load in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
25	Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue	Effective capacitance for gate delay with RC loads.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
25	Yu-Ting Pai, Yu-Kumg Chen	The Fastest Carry Lookahead Adder.	DELTA	2004	DBLP DOI BibTeX RDF	central processing unit, integrated circuit, adder, gate delay, carry lookahead adder
25	Wei-Yu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
25	Kanji Hirabayashi	Delay fault simulation of sequential circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	sequential circuit, fault simulation, robust test, Gate delay fault
25	Vineet Agarwal, Jin Sun 0006, Alexander V. Mitev, Janet Meiling Wang	Delay Uncertainty Reduction by Interconnect and Gate Splitting.	ASP-DAC	2007	DBLP DOI BibTeX RDF
25	Xijiang Lin, Janusz Rajski	Propagation delay fault: a new fault model to test delay faults.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam	Static Transition Probability Analysis Under Uncertainty.	ICCD	2004	DBLP DOI BibTeX RDF
25	Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar	Convex delay models for transistor sizing.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
25	Sorin Cotofana, Stamatis Vassiliadis	On the Design Complexity of the Issue Logic of Superscalar Machines.	EUROMICRO	1998	DBLP DOI BibTeX RDF
24	Kwangok Jeong, Andrew B. Kahng, Hailong Yao	Revisiting the linear programming framework for leakage power vs. performance optimization.	ISQED	2009	DBLP DOI BibTeX RDF
24	Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand	Delay Testing Viability of Gate Oxide Short Defects.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	gate oxide short (GOS), VLSI, delay testing, defect
24	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Parameterized block-based non-gaussian statistical gate timing analysis.	ASP-DAC	2006	DBLP DOI BibTeX RDF
24	Per Larsson-Edefors	Technology mapping onto very-high-speed standard CMOS hardware.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
23	Hidetoshi Matsumura, Atsushi Takahashi 0001	Delay variation tolerant clock scheduling for semi-synchronous circuits.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
23	Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang	Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.	DFT	2002	DBLP DOI BibTeX RDF
23	Taizhi Liu, Chang-Chih Chen, Soonyoung Cha, Linda Milor	System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
23	Halil Kükner, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken	Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
23	Tomohiro Yoshida, Kengo Kobayashi, Taiichi Otsuji, Tetsuya Suemitsu	Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs.	ESSDERC	2013	DBLP DOI BibTeX RDF
23	Halil Kukner, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken	Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.	DSD	2012	DBLP DOI BibTeX RDF
23	Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera	Statistical Gate-Delay Modeling with Intra-Gate Variability.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
23	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	A Statistical Gate-Delay Model Considering Intra-Gate Variability.	ICCAD	2003	DBLP DOI BibTeX RDF
23	Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar	A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
22	Kanupriya Gulati, Sunil P. Khatri	Accelerating statistical static timing analysis using graphics processing units.	ASP-DAC	2009	DBLP DOI BibTeX RDF
22	Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham	Analytical model for the impact of multiple input switching noise on timing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
22	David S. Kung 0001, Ruchir Puri	Optimal P/N width ratio selection for standard cell libraries.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow	A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
22	Zuying Luo	General transistor-level methodology on VLSI low-power design.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	nanometer, transistor level, simulation, optimization
22	Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd	A New Method for Design of Robust Digital Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
21	Ravi Bonam, Yong-Bin Kim, Minsu Choi	Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture.	DFT	2007	DBLP DOI BibTeX RDF
21	Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III	A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.	ARVLSI	1995	DBLP DOI BibTeX RDF	high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron
20	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Statistical Timing Analysis in the Presence of Signal-Integrity Effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
20	M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf	The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
20	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
20	Srinivas Devadas, Kurt Keutzer	Synthesis of robust delay-fault-testable circuits: theory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
20	Peng Li 0001, Zhuo Feng, Emrah Acar	Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
20	Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen	Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model.	DAC	2005	DBLP DOI BibTeX RDF
19	Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001	Statistical Timing Yield Optimization by Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
19	Frank Sill, Frank Grassert, Dirk Timmermann	Total leakage power optimization with improved mixed gates.	SBCCI	2005	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
19	Arash Reyhani-Masoleh, M. Anwar Hasan	Efficient digit-serial normal basis multipliers over binary extension fields.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	security, finite field, normal basis, Digit-serial multiplier
19	Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
19	Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults.	ISVLSI	2014	DBLP DOI BibTeX RDF
19	Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.	DFT	2011	DBLP DOI BibTeX RDF
19	Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal	Delay fault simulation with bounded gate delay mode.	ITC	2007	DBLP DOI BibTeX RDF
19	Yukio Okuda	Gate delay ratio model for unified path delay analysis.	ITC	2007	DBLP DOI BibTeX RDF
19	Andrzej Krasniewski, Leszek B. Wronski	Tests for path delay faults vs. tests for gate delay faults: how different they are.	EURO-DAC	1994	DBLP DOI BibTeX RDF
19	Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani	0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Ivan E. Sutherland, Jon K. Lexau	Designing Fast Asynchronous Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
18	Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	signal slope, interconnect, gate delay, subthreshold operation
18	Dennis Sylvester, Kurt Keutzer	Getting to the bottom of deep submicron.	ICCAD	1998	DBLP DOI BibTeX RDF	ASIC, power dissipation, signal integrity, interconnect modeling, wirelength, gate delay, CMOS scaling
18	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
18	Zaifu Zhang, Robert D. McLeod, Witold Pedrycz	A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	stuck-open and gate delay faults, Neural networks, test pattern generation
18	Nhon T. Quach, Michael J. Flynn	High-Speed Addition in CMOS.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit
18	Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro	Crosstalk Aware Static Timing Analysis: A Two Step Approach.	ISQED	2000	DBLP DOI BibTeX RDF