Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Hussein G. Badr, David Gelernter, Sunil Podar	An Adaptive Communications Protocol for Network Computers.	SIGMETRICS	1985	DBLP DOI BibTeX RDF
57	Volkhard Klinger	DiPaCS: a new concept for parallel circuit simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	DiPaCS system, parallel circuit simulation, distributed parallel circuit simulator, integrated circuit simulation, hierarchical circuit simulator, parallel processing, parallel programming, iterative methods, parallel machines, circuit analysis computing, integrated circuit layout, multicomputer systems, parallel iterative method
54	Dominik Stoffel, Wolfgang Kunz	Record & play: a structural fixed point iteration for sequential circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
50	Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu	Circuit optimization via adjoint Lagrangians.	ICCAD	1997	DBLP DOI BibTeX RDF	Adjoint circuit, Optimization, Circuit simulation, Trust region, Augmented Lagrangian, Circuit tuning
48	Pablo Molinero-Fernández, Nick McKeown	The performance of circuit switching in the internet.	Comput. Commun. Rev.	2002	DBLP DOI BibTeX RDF
48	Eric Felt, Alberto L. Sangiovanni-Vincentelli	Optimization of analog IC test structures.	VTS	1996	DBLP DOI BibTeX RDF	integrated circuit measurement, analog IC test structures, circuit parameters, statistical analysis, integrated circuit testing, accuracy, circuit optimisation, design of experiments, design of experiments, analogue integrated circuits, statistical techniques, network parameters, integrated circuit noise, measurement noise
47	Hideaki Doi, Yoko Suzuki, Yasuhiko Hara, Tadashi Iida, Yasuhiro Fujishita, Koichi Karasaki	Real-Time X-Ray Inspection of 3D Defects in Circuit Board Patterns.	ICCV	1995	DBLP DOI BibTeX RDF	printed circuit layout, X-ray applications, real time X-ray inspection, real-time X-ray inspection, 3D defect, 3-D defects, circuit board patterns, three dimensional defects, fine PCB patterns, sphere surface, X-ray detector, defect detection algorithm, heavy shading, real-time systems, feature extraction, feature extraction, signal processing, inspection, circuit analysis computing, X-ray images, printed circuit board, printed circuit testing, perspective transform, intensity variation, defect detection techniques
45	Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient
45	Narayanan Vijaykrishnan, N. Ranganathan	SUBGEN: a genetic approach for subcircuit extraction.	VLSI Design	1996	DBLP DOI BibTeX RDF	SUBGEN model, subcircuit extraction, large circuit graph, genetic algorithms, genetic algorithm, graph theory, computer-aided design, integrated circuit design, circuit CAD, CMOS integrated circuits, CMOS circuit, integrated circuit modelling
44	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	adiabatic logic circuit, power supply circuit, CMOS, dynamic circuit, low power circuit
43	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
43	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
42	Paul Tarau, Brenda Luderman	A Logic Programming Framework for Combinational Circuit Synthesis.	ICLP	2007	DBLP DOI BibTeX RDF	logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis
42	Jin-Tai Yan	Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning.	ICCD	1995	DBLP DOI BibTeX RDF	fuzzy neural nets, connection-oriented net model, fuzzy clustering techniques, K-way circuit partitioning, chain net model, cut analysis, multiple-pin net, edge-weighted graph, MCNC circuit benchmarks, partitioning balance, partitioning cut, computational complexity, complexity, fuzzy logic, high level synthesis, circuit analysis computing, hypergraph, fuzzy c-means clustering, mapped graph, fuzzy memberships
42	Jin-Tai Yan, Pei-Yung Hsiao	A new fuzzy-clustering-based approach for two-way circuit partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	fuzzy-clustering-based approach, two-way circuit partitioning, circuit netlist, undirected edge-weighted graph, tree net model, clustering distance, area information, area-balanced constraints, circuit benchmarks, VLSI, simulated annealing, network topology, trees (mathematics), fuzzy set theory, logic partitioning, fuzzy c-means clustering, fuzzy memberships
42	Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia N. Sanda	Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache
41	Yu Yu, Jussipekka Leiwo, A. Benjamin Premkumar	Hiding Circuit Topology from Unbounded Reverse Engineers.	ACISP	2006	DBLP DOI BibTeX RDF
41	Arun N. Lokanathan, Jay B. Brockman	A methodology for concurrent process-circuit optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
40	Sumit Roy 0003, Prithviraj Banerjee	A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis.	IPPS	1997	DBLP DOI BibTeX RDF	algebraic factorization, circuit replication, totally independent factorization, L-shaped partitioning strategy, rectangle interaction, ex1010 circuit, sequential kernel extraction algorithms, SIS sequential circuit synthesis system, quality degradation, parallel algorithms, logic synthesis, logic CAD, circuit partitions, divide-and-conquer strategy
40	Sachin S. Sapatnekar, Weitong Chuang	Power vs. delay in gate sizing: conflicting objectives?	ICCAD	1995	DBLP DOI BibTeX RDF	power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power
40	Fabian Vargas 0001, Alexandre M. Amory	Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transient-fault tolerant VHDL descriptions, area overhead analysis, reliable complex circuit design, harmful environments, reliability level, early-estimation, maximum area overhead, redundancy insertion, application minimum reliability requirement, FT-PRO tool, fault tolerant computing, redundancy, microprocessor, integrated circuit design, circuit CAD, CAD tool, transients, reliability estimation, memory elements, integrated circuit reliability, fault-tolerant circuit
40	Wolfgang Borutzky	Combining Behavioral Block Diagram Modelling with Circuit Simulation.	EUROCAST	1989	DBLP DOI BibTeX RDF	mixed behavioral, circuit-level modelling, electrical macromodels, continuous system simulation, electronic control systems, circuit simulation, functional simulation, block diagrams, signal processing systems
39	Kai Strunz, Qianli Su	Stochastic formulation of SPICE-type electronic circuit simulation with polynomial chaos.	ACM Trans. Model. Comput. Simul.	2008	DBLP DOI BibTeX RDF	Galerkin projection, electronic circuit, nonsampling stochastic analysis, tolerance analysis, SPICE, circuit simulation, spectral methods, transients, power electronics, stochastic differential equations, polynomial chaos, Circuit modeling
39	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
39	S. K. Gupta, M. M. Hasan	KANSYS: a CAD tool for analog circuit synthesis.	VLSI Design	1996	DBLP DOI BibTeX RDF	KANSYS, analog circuit synthesis, knowledge intensive hierarchical design, transistor circuit designs, functional circuits, knowledge based systems, hierarchy, integrated circuit design, circuit CAD, CAD tool, analogue integrated circuits, design knowledge, process specifications
38	Manoj Franklin	Fast computation of C-MISR signatures.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits
37	Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar	Testability-oriented channel routing.	VLSI Design	1995	DBLP DOI BibTeX RDF	IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield
37	Naim Ben-Hamida, Bechir Ayari, Bozena Kaminska	Testing of embedded A/D converters in mixed-signal circuit.	ICCD	1996	DBLP DOI BibTeX RDF	embedded A/D converters testing, integral nonlinearity error, differential nonlinearity error, offset error, gain error, boolean function manipulation, FFT, histogram, functional testing, transfer function, digital circuit, signal-to-noise ratio, mixed-signal circuit, analogue-digital conversion
37	Akio Okazaki, Takashi Kondo, Kazuhiro Mori, Shou Tsunekawa, Eiji Kawamoto	An Automatic Circuit Diagram Reader with Loop-Structure-Based Symbol Recognition.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	automatic circuit diagram reader, loop-structure-based symbol recognition, logic circuit diagram reader, symbol segmentation, symbol identification, decision-tree control, character string recognition, connecting line analysis, computer vision, feature extraction, computerised pattern recognition, computerised pattern recognition, logic CAD, template matching, circuit CAD, VLSI-CAD
36	Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles	How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.	ISQED	2005	DBLP DOI BibTeX RDF
36	S. C. Prasad, Kaushik Roy 0001	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
36	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
36	Keying Wu, P. K. H. Ng, Xing Dong Jia, Richard M. M. Chen, A. M. Layfield	Performance tuning of a multiprocessor sparse matrix equation solver.	HICSS (1)	1995	DBLP DOI BibTeX RDF	multiprocessor sparse matrix equation solver, sparse matrix equation, linear simultaneous equations, electrical circuit, multiprocessor implementation, parallel direct method, parallel algorithms, circuit analysis computing, SPICE, SPICE, circuit simulation, sparse matrices, performance tuning
35	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
35	Anantha P. Chandrakasan	Ultra low power digital signal processing.	VLSI Design	1996	DBLP DOI BibTeX RDF	ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
35	Trevor J. Smedley	A High-Level Visual Language for the Graphical Description of Digital Circuits.	VL	1995	DBLP DOI BibTeX RDF	pulse circuits, high-level visual language, graphical description, programming language systems, digital design systems, full-featured visual programming language, complex circuit specification, repetitive structures, conditional structures, visual languages, circuit analysis computing, circuit CAD, digital circuits, engineering graphics, program structures, digital circuit design
35	L. F. Fuller, C. Kraaijenvanger	Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education
35	Zhiyuan Cai, Shaohua Ma, Yangyang Ge, Erzhi Wang	Time Series Prediction of Short Circuit Current for Synchronous Control of Synthetic Test Based on Delay Coordinate Embedding.	ICIC (3)	2007	DBLP DOI BibTeX RDF	short circuit current, synthetic test, time series prediction, synchronous control
35	Di Long, Xianlong Hong, Sheqin Dong	Signal-path driven partition and placement for analog circuit.	ASP-DAC	2006	DBLP DOI BibTeX RDF	analog placement, device merging, layout automation, signal-path, symmetry constrain, circuit partition
35	Mohamed A. El-Gamal, Hany L. Abdel-Malek, M. A. Sorour	A neural-network-based approach for post-fabrication circuit tuning.	Neural Comput. Appl.	2005	DBLP DOI BibTeX RDF	Clustering, Neural networks, Feature selection, Self organizing maps, Circuit tuning
35	Liming Cai, Jianer Chen, Johan Håstad	Circuit Bottom Fan-in and Computational Power.	CCC	1997	DBLP DOI BibTeX RDF	computational complexity, lower bound, circuit complexity, alternating Turing machine
35	Hajime Shibata, Adrian Stoica, Nobuo Fujii	Controllable decoding for automated analog circuit structure design.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Automated circuit synthesis, Genetic algorithm, Analog circuit
34	Paul Tarau, Brenda Luderman	Revisiting exact combinational circuit synthesis.	SAC	2008	DBLP DOI BibTeX RDF	exact combinational circuit synthesis, logic programming and circuit design, minimal transistor-count circuit synthesis
34	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	Boolean process-an analytical approach to circuit representation (II).	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	waveform analysis, circuit representation, logical behavior, waveform functions, mathematical tools, waveform polynomials, input transitions, VLSI, Boolean functions, timing, design for testability, logic design, logical design, polynomials, integrated circuit design, VLSI circuits, performance enhancement, timing behavior, Boolean process, circuit delay
34	Imtiaz P. Shaik, Michael L. Bushnell	Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .	VTS	1995	DBLP DOI BibTeX RDF	low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
33	Pierre Fraigniaud, Joseph G. Peters	Structured communication in torus networks.	HICSS (2)	1995	DBLP DOI BibTeX RDF	combinational switching, structured communication, one-to-all data movement patterns, all-to-all data movement patterns, 2D tori, multi-dimensional tori, synchronous circuit-switched routing, multi-scattering, circuit-switching algorithms, short routing, broadcasting, broadcasting, multiprocessor interconnection networks, gossiping, distributed memory systems, network routing, virtual channels, cycles, circuit switching, switching theory, scattering, torus networks, message length, store-and-forward routing
33	Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti	Circuit-Switched Coherence.	NOCS	2008	DBLP DOI BibTeX RDF	Interconnection network, multiprocessor systems, cache coherence
33	Daijue Tang, Sharad Malik	Solving Quantified Boolean Formulas with Circuit Observability Don't Cares.	SAT	2006	DBLP DOI BibTeX RDF
33	Tadayoshi Enomoto, Nobuaki Kobayashi	A low dynamic power and low leakage power CMOS square-root circuit.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
33	Xinghao Chen 0003, Michael L. Bushnell	Sequential circuit test generation using dynamic justification equivalence.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	search decision spaces, test generation efficiency, automatic test pattern generation, stuck-at faults, justification
33	Abby A. Ilumoka	Efficient prediction of interconnect crosstalk using neural networks.	ICTAI	2000	DBLP DOI BibTeX RDF	interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration
33	Carlton Bickford, Marie S. Teo, Gary Wallace, John A. Stankovic, Krithi Ramamritham	A robotic assembly application on the Spring real-time system.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	printed circuit manufacture, printed circuit layout, robotic assembly application, Spring real-time system, run-time system support, predictability demands, robotic work-cell, circuit board assembly, user understanding, target hardware properties, process layout, resource layout, shared resource usage, process suspension, efficient run-time representation, real-time systems, robots, timing, completeness, flexibility, reengineering, timing analysis, circuit layout CAD, assembling, systems re-engineering, interprocess communication, program representation, porting, ease of use, industrial robots, software development tools
33	Pradip Mandal, V. Visvanathan	Design of high performance two stage CMOS cascode op-amps with stable biasing.	VLSI Design	1996	DBLP DOI BibTeX RDF	two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability
33	J. T. Mowchenko, Y. Yang	Optimizing wiring space in slicing floorplans.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	wiring space optimisation, slicing floorplans, net density, sibling rectangles, circuit modules, routed layouts, VLSI, heuristic, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, branch and bound algorithm, wiring, IC layout
32	Che-Wei Lin, Jeen-Shing Wang, Chun-Chang Yu, Ting-Yu Chen	Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network.	ICIC (2)	2007	DBLP DOI BibTeX RDF	Synchronous pipeline design, neuro-fuzzy circuit, FPGA
32	Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III	Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.	DATE	1998	DBLP DOI BibTeX RDF	signature-invariance, circuit mutants, benchmarking, equivalence class
32	Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara	Sequential Test Generation Based on Circuit Pseudo-Transformation.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	acyclic structure, circuit pseudo-transformations, test generation, Sequential circuits, balanced structure
32	Zhai Zhang, Youren Wang, Shanshan Yang, Rui Yao, Jiang Cui	The research of self-repairing digital circuit based on embryonic cellular array.	Neural Comput. Appl.	2008	DBLP DOI BibTeX RDF	Self-repairing digital circuit, Embryonic cellular array, Fault-tolerance design, Digital circuit design
32	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Modeling and analysis of circuit performance of ballistic CNFET.	DAC	2006	DBLP DOI BibTeX RDF	ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance
32	Wilbert H. F. J. Körver	A universal formalization of the effects of threshold voltages for discrete switch-level circuit models.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits
32	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
32	Lluís Ribas, Jordi Carrabina	Digital MOS Circuit Partitioning with Symbolic Modeling.	DATE	1999	DBLP DOI BibTeX RDF	switch-level circuit analysis, symbolic circuit traversal, circuit partitioning, symbolic modeling
32	F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak	Analog circuit simulation and troubleshooting with FLAMES.	VTS	1996	DBLP DOI BibTeX RDF	analog circuit simulation, model-based expert system, VLSI, fuzzy logic, fuzzy logic, integrated circuit testing, circuit analysis computing, analogue integrated circuits, troubleshooting, diagnostic expert systems, FLAMES
32	Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs	Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
31	Cheng-Shang Chang, Duan-Shin Lee	Quasi-circuit switching and quasi-circuit switches.	ITRE	2005	DBLP DOI BibTeX RDF
31	Benno H. Krabbenborg, A. Bosma, Henk C. de Graaff, Ton J. Mouthaan	Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
31	Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004	IR-drop Reduction Through Combinational Circuit Partitioning.	PATMOS	2006	DBLP DOI BibTeX RDF	Static Timing Analysis, IR-drop, circuit partitioning
30	Anirudh Devgan	Efficient coupled noise estimation for on-chip interconnects.	ICCAD	1997	DBLP DOI BibTeX RDF	coupled noise estimation, dynamic logic circuit families, noise criticality pruning, physical design based noise avoidance, circuit simulation, on-chip interconnects, Elmore delay, noise analysis, timing simulation, integrated circuit noise, deep submicron design
30	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
30	Amir H. Farrahi, Majid Sarrafzadeh	System partitioning to maximize sleep time.	ICCAD	1995	DBLP DOI BibTeX RDF	Geo-Part, exploitable sleep time, geometric partitioning heuristic, low-power synthesis, memory refresh circuitry, segment tree data structure, VLSI, logic CAD, integrated circuit design, circuit CAD, circuit optimisation, logic partitioning, partitioning problem, system partitioning
30	Yasuhiko Hara, Hideaki Doi, Koichi Karasaki, Tadashi Iida	A System for PCB Automated Inspection Using Fluorescent Light.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	violet illumination, PCB automated inspection, fluorescent light, nicks, printed circuit board pattern, ultraviolet rays, glass-epoxy, glass-polyimide, high-sensitivity TV camera, silhouette image, fluorescence, pattern recognition, computer vision, computer vision, fault detection, computerised pattern recognition, inspection, circuit analysis computing, fault location, cuts, printed circuit testing, optical fiber, short-circuits
30	Yinlei Yu, Cameron Brien, Sharad Malik	Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Zhaohui Fu, Sharad Malik	Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Sheldon X.-D. Tan	A general hierarchical circuit modeling and simulation algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
30	Zhaohui Fu, Yinlei Yu, Sharad Malik	Considering Circuit Observability Don't Cares in CNF Satisfiability.	DATE	2005	DBLP DOI BibTeX RDF
30	Tatiana Kalganova, Julian F. Miller	Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-Objective Fitness.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
30	Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.	DFT	1997	DBLP DOI BibTeX RDF	defect-tolerant circuit, contamination, wafer test, silicon chip, reconfiguration, redundancy, integrated circuit testing, manufacturing, yield, cost model, integrated circuit, figure of merit, fault tolerant circuit
30	Vamsi Boppana, W. Kent Fuchs	Integrated fault diagnosis targeting reduced simulation.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS 85 circuit, ISCAS 89 circuit, dynamic techniques, integrated fault diagnosis, precomputed information, reduced simulation, run-time cost reduction, static techniques, combinational circuit, circuit analysis computing, run-time analysis
30	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
30	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
30	Takushi Tanaka	Parsing Electronic Circuits in a Logic Grammar.	IEEE Trans. Knowl. Data Eng.	1993	DBLP DOI BibTeX RDF	trouble shooting, automatic circuit understanding, circuit structures, definite clause set grammar, DCSG top-down parsing mechanism, trees (mathematics), circuit analysis computing, grammars, structural analysis, formal logic, hierarchical structures, circuit design, words, parse trees, functional blocks, causal analysis, sentence, logic grammar
30	Rohit Kapur, M. Ray Mercer	Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	bounding algorithm, circuit faults, conditional syndromes, auxiliary gate, pseudorandom pattern resistant faults, circuit structure, computational complexity, lower bounds, built-in self test, integrated circuit testing, circuit analysis computing, signal probabilities, testability measurement, random pattern testability
30	Chris C. N. Chu, D. F. Wong 0001	VLSI Circuit Performance Optimization by Geometric Programming.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing
29	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
29	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	Testing for the programming circuit of LUT-based FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table
29	Andy Negoi, Alain Guyot, Jacques Zimmermann	A dedicated circuit for charged particles simulation using the Monte Carlo method.	ASAP	1997	DBLP DOI BibTeX RDF	dedicated circuit, charged particles simulation, dedicated integrated circuit, integro-differential Boltzmann equation, direct statistical computation, simulated particles distribution function, semiconductor device hardware simulator, microdynamical transport, Boltzmann equation, binary format, drift velocity, static uniform electric field, hot carrier effects, computational complexity, Monte Carlo method
29	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
29	Saket Srivastava, Sanjukta Bhanja	Hierarchical Probabilistic Macromodeling for QCA Circuits.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	QCA computing, QCA macromodel, Bayesian networks, Quantum-dot Cellular Automata, probabilistic computing
29	Srimat T. Chakradhar, Sujit Dey	Resynthesis and retiming for optimum partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
29	Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang	QuteSAT: a robust circuit-based SAT solver for complex circuit structure.	DATE	2007	DBLP DOI BibTeX RDF
28	Humberto Campanella, Arantxa Uranga, Pascal Nouet, Pedro De Paco Sanchez, Núria Barniol, Jaume Esteve	Instantaneous de-embedding of the on-wafer equivalent-circuit parameters of acoustic resonator (FBAR) for integrated circuit applications.	SBCCI	2007	DBLP DOI BibTeX RDF	RF circuit design, parameter extraction and fitting, thin-film bulk acoustic wave resonators (FBAR), MEMS
28	Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia	Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF	Diode-resistor logic, logic-level degradation, nano-crossbar circuit, robust circuit design
28	Jia Di, Parag K. Lala	Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit
28	Russell Impagliazzo	Can every randomized algorithm be derandomized?	STOC	2006	DBLP DOI BibTeX RDF	algebraic circuit complexity, probabilistic algorithms, derandomization, circuit complexity, complexity classes, pseudo-randomness
28	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
28	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
28	Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
28	Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana	CODAC-a characterization system for digital and analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	CODAC, characterization system, electrical simulator, procedural interface, customized analysis functions, parallel processing, circuit analysis computing, Monte Carlo methods, circuit CAD, SPICE, SPICE, analog circuits, digital circuits, CAD tool, digital integrated circuits, analogue integrated circuits, circuit analysis, Monte Carlo analysis
28	Sven Simon 0001, Ralf Bucher, Josef A. Nossek	Retiming of synchronous circuits with variable topology.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits
28	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models