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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4291 occurrences of 2038 keywords
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Results
Found 4273 publication records. Showing 4273 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
52 | Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 393-402, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair |
50 | Jason P. Hurst, Adit D. Singh |
A differential built-in current sensor design for high speed IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 419-423, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices |
45 | Peter D. Hortensius, Robert D. McLeod, Howard C. Card |
Cellular Automata-Based Signature analysis for Built-in Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(10), pp. 1273-1283, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
signature analysis properties, one-dimensional cellular automata, cyclic-group rules, CALBO, cellular automata-based logic block observation, BILBO, built-in block observation, logic testing, built-in self-test, built-in self test, LFSR, linear feedback shift register, finite automata, test pattern generation |
41 | Hardy J. Pottinger, Chien-Yuh Lin |
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 242-245, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education |
38 | Da-Ming Chang, Jin-Fu Li 0001, Yu-Jen Huang |
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 181-192, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Built-in self-repair (BISR), Built-in redundancy-analysis (BIRA), Two-level redundancy, Random access memory, System-on-chip (SOC) |
38 | Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin |
A built-in self-test and self-diagnosis scheme for embedded SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 45-50, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM |
36 | Sying-Jyan Wang, Chen-Jung Wei |
Efficient built-in self-test algorithm for memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 66-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips |
36 | K. Y. Ko, Mike W. T. Wong |
New built-in self-test technique based on addition/subtraction of selected node voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 39-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
node voltages, built-in self test, built-in self-test, fault detection, fault location, analogue circuits |
36 | Paul Chang, Brion L. Keller, Sarala Paliwal |
Effective parallel processing techniques for the generation of test data for a logic built-in self test system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 374-379, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data |
36 | Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici |
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 387-392, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing |
36 | Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi |
Low-cost DC built-in self-test of linear analog circuits using checksums. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 230-233, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes |
36 | Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer |
Arithmetic built-in self test for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 132-139, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage |
33 | R. K. Sharma, Aditi Sood |
Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAP ![In: 2010 International Conference on Signal Acquisition and Processing, ICSAP 2010, Bangalore, India, February 9-10, 2010, pp. 8-12, 2010, IEEE Computer Society, 978-0-7695-3960-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Defect-Per Million (DPM), Memory Built-in Self Test (MBIST), Microcoded MBIST, MUT (Memory Under Test), Built-In Self Test (BIST) |
33 | T. Haulin |
Built-in parametric test for controlled impedance I/Os. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 123-129, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
controlled impedance I/Os, built-in parametric test, full DC parametrics, full speed AC tests, lower cost ATE, differential signal I/Os, single-ended signal I/Os, short circuit proof drivers, B9 test method, bidirectional I/O, differential receivers, differential transmitters, diagnostic tests, narrow pulse test, contact test, high speed test logic, built-in self test, functional test, boundary scan, static tests |
33 | Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak |
An improved output compaction technique for built-in self-test in VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 403-407, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits |
33 | Kozo Kinoshita, Kewal K. Saluja |
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(10), pp. 862-870, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity |
32 | Chengying Mao, Yansheng Lu, Jinlong Zhang |
Regression testing for component-based software via built-in test design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007, pp. 1416-1421, 2007, ACM, 1-59593-480-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
built-in test design, method call graph, component, regression testing, test case selection |
32 | Abhijit Chatterjee, Jacob A. Abraham |
Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(4), pp. 351-372, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test |
30 | Kanad Chakraborty |
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 89-108, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth |
30 | Dimitrios Kagaris, Spyros Tragoudas |
Generating deterministic unordered test patterns with counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 374-379, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
counting circuits, deterministic unordered test patterns, counter-based schemes, built-in mechanisms, test pattern generation session, ISCAS'85 benchmarks, logic testing, built-in self test, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, hardware overhead |
30 | Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu |
Economic Aspects of Memory Built-in Self-Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 164-172, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair |
29 | Yingwu Zhu, Yiming Hu |
Disk Built-in Caches: Evaluation on System Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 11th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2003), 12-15 October 2003, Orlando, FL, USA, pp. 306-, 2003, IEEE Computer Society, 0-7695-2039-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Colin Atkinson 0001 |
Component-Oriented Verification of Software Architectures through Built-in Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECSA ![In: Software Architecture, Second European Conference, ECSA 2008, Paphos, Cyprus, September 29 - October 1, 2008, Proceedings, pp. 2, 2008, Springer, 978-3-540-88029-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Verification, built-in tests, system services |
27 | Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret |
A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 151-158, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-In current sensor |
27 | Jonathan Vincent, Graham King, Peter Lay, John Kinghorn |
Principles of Built-In-Test for Run-Time-Testability in Component-Based Software Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 10(2), pp. 115-133, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
continuous test, component based software engineering, built-in-test, verification and validation |
27 | Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee |
Built-in current sensor designs based on the bulk-driven technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 384-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement |
27 | Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai |
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 100-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits |
27 | Wojciech Maly, Marek J. Patyra |
Design of ICs applying built-in current testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 397-406, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
BIC-testing, Built-in testing, current testing |
26 | Yavuz Kiliç, Mark Zwolinski |
Process variation independent built-in current sensor for analogue built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 398-401, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu |
Diagonal Test and Diagnostic Schemes for Flash Memorie. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 37-46, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
built-in self-diagnosis (BISD), memory diagnosis, built-in self-test (BIST), flash memory, memory testing, system-on-chip (SOC) |
25 | Wei-Lun Wang, Kuen-Jong Lee |
Accelerated test pattern generators for mixed-mode BIST environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 368-373, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics |
25 | Der-Cheng Huang, Wen-Ben Jone |
An efficient parallel transparent diagnostic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 299-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
parallel transparent diagnostic BIST, built-in self-diagnosis method, multiple embedded memory arrays, transparent diagnostic interface, redundant read/write/shift operations, march algorithm, TDiagRSMarch algorithm, low hardware overhead, test time reduction, diagnostic efficiency, parallel algorithms, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic testing, test coverage, integrated memory circuits |
25 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for faults in system backplanes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 406-413, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration |
25 | Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi |
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 261-266, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits |
25 | Christian Dufaza, Hassan Ihs |
A BIST-DFT technique for DC test of analog modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(1-2), pp. 117-133, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST |
25 | Dimitrios Kagaris, Spyros Tragoudas |
A multiseed counter TPG with performance guarantee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 34-39, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation |
25 | T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael |
Faulty chip identification in a multi chip module system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 254-259, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules |
25 | Mehdi Ehsanian, Bozena Kaminska, Karim Arabi |
A new digital test approach for analog-to-digital converter testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 60-65, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion |
25 | Nur A. Touba, Edward J. McCluskey |
Applying two-pattern tests using scan-mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 393-399, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests |
25 | Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska |
Design and performance of CMOS TSPC cells for high speed pseudo random testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 368-373, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists |
25 | Manoj Franklin |
Fast computation of C-MISR signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 293-297, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits |
25 | Joan Carletta, Christos A. Papachristou |
Testability analysis and insertion for RTL circuits based on pseudorandom BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 162-167, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits |
25 | Imtiaz P. Shaik, Michael L. Bushnell |
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 393-399, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions |
25 | Javier Argüelles, MarÃa José López, J. Blanco, Mar MartÃnez, Salvador Bracho |
Iddt testing of continuous-time filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 101-107, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
continuous time filters, continuous-time filters, design-for-test methodology, dynamic supply current consumption, dynamic current, partitioning methodology, test reliability, built-in self test, integrated circuit testing, design for testability, automatic testing, CMOS, automatic test equipment, built-in current sensor, CMOS analogue integrated circuits |
25 | Jacob Savir |
On shrinking wide compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 108-117, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers |
25 | Joan Carletta, Christos A. Papachristou |
Structural constraints for circular self-test paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 486-491, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits |
25 | Albrecht P. Stroele |
Signature analysis and aliasing for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 118-124, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths |
25 | Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham |
Efficient multisine testing of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 234-238, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits |
25 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
25 | Laurent Leyssenne, Eric Kerherve, Yann Deval, Didier Belot |
A novel delta sigma built-in-current-sensor as a signal strength indicator for RF transceiver reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RF power amplifier, efficiency maximization, WLAN, built-in current sensor, delta-sigma modulation |
25 | Wimol San-Um, Masayoshi Tachibana |
Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test |
25 | Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt |
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(5), pp. 425-437, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Fault-tolerance, Reliability, Testing, Built-in tests, Error-checking |
25 | Alodeep Sanyal, Sandip Kundu |
A Built-in Test and Characterization Method for Circuit Marginality Related Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 838-843, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR) |
25 | Chen-Wei Lin, Jiun-Lang Huang |
A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 169-174, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
TFT array, charge sensing, system-on-panel, built-in self-test, LTPS |
25 | Jiang Shi, Ricky Smith |
Built-In Self-Test for Embedded Voltage Regulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 133-136, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
voltage output, current loading, built-in, embedded, manufacturing, regulator, self-test |
25 | Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret |
A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(6), pp. 593-603, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-in current sensor |
25 | Daniel Brenner, Colin Atkinson 0001, Rainer Malaka, Matthias Merdes, Barbara Paech, Dima Suliman |
Reducing verification effort in component-based software engineering through built-in testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Syst. Frontiers ![In: Inf. Syst. Frontiers 9(2-3), pp. 151-162, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Run-time testing, MORABIT, Built-in test, Integration test |
25 | Egas Henes Neto, Fernanda Lima Kastensmidt, Gilson I. Wirth |
A built-in current sensor for high speed soft errors detection robust to process and temperature variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 190-195, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault-tolerance, process variations, built-in current sensor |
25 | Barend Köbben |
RIMapperWMS: a Web Map Service providing SVG maps with a built-in client. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AGILE Conf. ![In: The European Information Society: Leading the Way with Geo-information, Proceedings of the 10th AGILE Conference, Aalborg, Denmark, 8-11 May 2007, pp. 217-230, 2007, Springer, 978-3-540-72384-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
built-in GUI, Spatial Databases, SVG, WMS, Web Mapping |
25 | Khoa Nguyen Tran, Zhiyong Huang |
Design and implementation of a built-in camera based user interface for mobile games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GRAPHITE ![In: Proceedings of the 5th International Conference on Computer Graphics and Interactive Techniques in Australasia and Southeast Asia 2007, Perth, Western Australia, 1-4 December 2007, pp. 25-31, 2007, ACM, 978-1-59593-912-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
built-in camera, user interfaces, augmented reality, mobile devices, motion detection, mobile games |
25 | Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt |
Using Bulk Built-in Current Sensors to Detect Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(5), pp. 10-18, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Reliability, Built-in tests, Error-checking, Testing and Fault-Tolerance |
25 | Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 449-462, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array |
25 | Kentaroh Katoh, Hideo Ito |
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 69-74, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT |
25 | Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-MartÃnez, Edgar Sánchez-Sinencio |
An On-Chip Spectrum Analyzer for Analog Built-In Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(3), pp. 205-219, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analog IC test, built-in testing, frequency response, switched-capacitor circuits |
25 | Yolanda Lechuga, Román Mozuelos, Miguel Angel Allende, Mar MartÃnez, Salvador Bracho |
Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(6), pp. 583-598, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
transient current test, fault detection, built-in current sensor, supply current monitoring |
25 | Bartomeu Alorda, Sebastià A. Bota, Jaume Segura 0001 |
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 177-182, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Current based testing, built-in current monitors, high-speed measurements, transient current |
25 | Vishal Suthar, Shantanu Dutt |
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 78-83, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability |
25 | Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar |
Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 753-756, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST |
25 | Dimitri Kagaris |
Built-In TPG with Designed Phaseshifts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 365-370, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Built-in Self-Test (BIST), Cellular Automata, Test Pattern Generation (TPG), Phase Shifters |
25 | Taewoong Jeon, Hyonwoo Seung, Sungyoung Lee |
Embedding built-in tests in hot spots of an object-oriented framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 37(8), pp. 25-34, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
hook classes, testability, object-oriented framework, built-in test (BIT) |
25 | Irith Pomeranz, Sudhakar M. Reddy |
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(11), pp. 1282-1293, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scan circuits, Built-in testing, Cartesian product |
25 | Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu |
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 515-527, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test |
25 | Yingxu Wang 0001, Graham King |
A European COTS Architecture with Built-in Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOIS ![In: Object-Oriented. Information Systems, 8th International Conference, OOIS 2002, Montpellier, France, September 2-5, 2002, Proceedings, pp. 336-347, 2002, Springer, 3-540-44087-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
test reuse, run-time testing, Software engineering, architecture, component, COTS, built-in tests, real-time software, industrial practices, OO |
25 | Itsuo Takanami |
Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 134-142, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
built-in selft-reconfiguration, digital neural circuit, direct spare replacement, fault-tolerance, mesh-connected processor array |
25 | Ilker Hamzaoglu, Janak H. Patel |
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 369-376, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model |
25 | Albrecht P. Stroele |
Synthesis for Arithmetic Built-In Self-Tes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 165-170, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator |
25 | Yukiya Miura, Hiroshi Yamazaki |
A Low-Loss Built-In Current Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 39-48, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low-voltage LSIs, multiple power supplies, IDDQ testing, Built-in current sensor |
25 | Yingxu Wang 0001, Graham King, Hakan Wickburg |
A Method for Built-in Tests in Component-based Software Maintenance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSMR ![In: 3rd European Conference on Software Maintenance and Reengineering (CSMR '99), 3-5 March 1999, Amsterdam, The Netherlands, pp. 186-189, 1999, IEEE Computer Society, 0-7695-0090-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
maintenance mode, normal mode, test component reuse, reengineering maintenance, Software engineering, software maintenance, software components, built-in test |
25 | Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy |
Built In Self Test for Ring Addressed FIFOs with Transparent Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 72-77, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Built In Self Test, Memory testing, Embedded memories |
25 | Christian Dufaza |
Multiple Paths Sensitization of Digital Oscillation Built-In Self Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 166-174, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
DOBIST, Test, Built-In Self Test |
25 | Paul Chang, Brion L. Keller, Sarala Paliwal |
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 175-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation |
25 | Y. Tsiatouhas, Th. Haniotakis |
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 95-100, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Built-In Self Test, Delay Fault Testing |
25 | Yu-Yau Guo, Jien-Chung Lo |
Challenges of Built-In Current Sensor Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 192-, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
voltage regulator, built-in current sensor, Current testing, decoupling capacitor |
25 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 205-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
25 | O. A. Petlin, Stephen B. Furber |
Built-In Self-Testing of Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 22-29, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Built-in self-test, Design for test, Asynchronous design, Micropipelines |
25 | Joseph C. W. Pang, Mike W. T. Wong, Yim-Shu Lee |
Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 82-87, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Built-in intermediate voltage sensor, bridging fault, totally self-checking circuit |
25 | Irith Pomeranz, Sudhakar M. Reddy |
Built-in test generation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 421-426, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
comparison units, built-in self-test, synchronous sequential circuits, at-speed test |
25 | Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis |
An efficient built-in self test method for robust path delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(2), pp. 219-222, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
two-pattern test generator, single-input change pattern testing, robust path delay faults, built-in self test |
25 | Josep Rius 0001, Joan Figueras |
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(3), pp. 295-310, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
I DDQ testability, Built-in Current Sensors, current testing |
25 | Marcelo Lubaszewski, Salvador Mir, Leandro Pulz |
ABILBO: Analog BuILt-in Block Observer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 600-603, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in self-test, design for test, analog and mixed-signal testing |
25 | Albrecht P. Stroele |
Arithmetic Pattern Generators for Built-In Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 131-134, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Arithmetic functions, built-in self-test, design for testability, pattern generator |
25 | Stephan P. Athan, David L. Landis, Sami A. Al-Arian |
A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 118-123, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices |
25 | Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik |
Integration of partial scan and built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 125-137, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
test points, built-in self-test, design for testability, partial scan |
25 | Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller |
Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(3), pp. 209-221, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
linear hybrid cellular automata, sequential fault, transition capability, built-in self-test, linear feedback shift register, linear finite state machine |
25 | Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis |
An efficient comparative concurrent Built-In Self-Test technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 309-315, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead |
23 | Davide Appello |
Session Abstract. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 240-241, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Probing technologies and probe cards, reduced pin count testing, multi-site efficiency, reconfigurable test resources and test resource partitioning, test generation and diagnosis, built-in and built-off DFT, test economics |
23 | C.-Y. Kuo, J.-L. Huang |
A Period Tracking Based On-Chip Sinusoidal Jitter Extraction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 400-405, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
sinusoidal jitter, jitter decomposition, built-in self-diagnosis, built-in self-test |
23 | Janusz Rajski, Jerzy Tyszer |
Recursive Pseudoexhaustive Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1517-1521, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
recursive pseudoexhaustive test pattern generation, parallel pattern generator, exclusive-or array, serial generators, scan-based built-in self-test, logic testing, built-in self test, test vectors, characteristic functions |
23 | John Y. Sayah, Charles R. Kime |
Test Scheduling in High Performance VLSI System Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(1), pp. 52-67, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
high performance VLSI system, parallel test execution, organization level, test parallelism, schedulability criteria, suboptimum heuristic-based algorithms, VLSI, built-in self-test, built-in self test, time, integrated circuit testing, design for testability, automatic testing, space, heuristic programming, test scheduling, inherent parallelism |
22 | Dusko Karaklajic, Miroslav Knezevic, Ingrid Verbauwhede |
Low Cost Built in Self Test for Public Key Crypto Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2010, Santa Barbara, California, USA, 21 August 2010, pp. 97-103, 2010, IEEE Computer Society, 978-0-7695-4169-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Security, Built-In Self-Test, Public-Key Cryptography, Pseudorandom Testing |
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