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1953-1978 (15) 1979-1982 (17) 1983-1984 (20) 1985 (19) 1986 (16) 1987 (26) 1988 (51) 1989 (29) 1990 (49) 1991 (36) 1992 (45) 1993 (55) 1994 (55) 1995 (98) 1996 (86) 1997 (98) 1998 (119) 1999 (128) 2000 (167) 2001 (153) 2002 (175) 2003 (197) 2004 (258) 2005 (268) 2006 (293) 2007 (328) 2008 (297) 2009 (189) 2010 (89) 2011 (71) 2012 (70) 2013 (55) 2014 (63) 2015 (66) 2016 (68) 2017 (73) 2018 (55) 2019 (75) 2020 (66) 2021 (77) 2022 (70) 2023 (74) 2024 (14)
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article(1288) book(4) incollection(12) inproceedings(2949) phdthesis(20)
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Found 4273 publication records. Showing 4273 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
52Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair
50Jason P. Hurst, Adit D. Singh A differential built-in current sensor design for high speed IDDQ testing. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
45Peter D. Hortensius, Robert D. McLeod, Howard C. Card Cellular Automata-Based Signature analysis for Built-in Self-Test. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF signature analysis properties, one-dimensional cellular automata, cyclic-group rules, CALBO, cellular automata-based logic block observation, BILBO, built-in block observation, logic testing, built-in self-test, built-in self test, LFSR, linear feedback shift register, finite automata, test pattern generation
41Hardy J. Pottinger, Chien-Yuh Lin Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
38Da-Ming Chang, Jin-Fu Li 0001, Yu-Jen Huang A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Built-in self-repair (BISR), Built-in redundancy-analysis (BIRA), Two-level redundancy, Random access memory, System-on-chip (SOC)
38Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin A built-in self-test and self-diagnosis scheme for embedded SRAM. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM
36Sying-Jyan Wang, Chen-Jung Wei Efficient built-in self-test algorithm for memory. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
36K. Y. Ko, Mike W. T. Wong New built-in self-test technique based on addition/subtraction of selected node voltages. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF node voltages, built-in self test, built-in self-test, fault detection, fault location, analogue circuits
36Paul Chang, Brion L. Keller, Sarala Paliwal Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
36Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
36Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi Low-cost DC built-in self-test of linear analog circuits using checksums. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes
36Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer Arithmetic built-in self test for high-level synthesis. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
33R. K. Sharma, Aditi Sood Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Faults. Search on Bibsonomy ICSAP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Defect-Per Million (DPM), Memory Built-in Self Test (MBIST), Microcoded MBIST, MUT (Memory Under Test), Built-In Self Test (BIST)
33T. Haulin Built-in parametric test for controlled impedance I/Os. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF controlled impedance I/Os, built-in parametric test, full DC parametrics, full speed AC tests, lower cost ATE, differential signal I/Os, single-ended signal I/Os, short circuit proof drivers, B9 test method, bidirectional I/O, differential receivers, differential transmitters, diagnostic tests, narrow pulse test, contact test, high speed test logic, built-in self test, functional test, boundary scan, static tests
33Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak An improved output compaction technique for built-in self-test in VLSI circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
33Kozo Kinoshita, Kewal K. Saluja Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1986 DBLP  DOI  BibTeX  RDF weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity
32Chengying Mao, Yansheng Lu, Jinlong Zhang Regression testing for component-based software via built-in test design. Search on Bibsonomy SAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF built-in test design, method call graph, component, regression testing, test case selection
32Abhijit Chatterjee, Jacob A. Abraham Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
30Kanad Chakraborty Testing and Reliability Techniques for High-Bandwidth Embedded RAMs. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
30Dimitrios Kagaris, Spyros Tragoudas Generating deterministic unordered test patterns with counters. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF counting circuits, deterministic unordered test patterns, counter-based schemes, built-in mechanisms, test pattern generation session, ISCAS'85 benchmarks, logic testing, built-in self test, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, hardware overhead
30Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu Economic Aspects of Memory Built-in Self-Repair. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair
29Yingwu Zhu, Yiming Hu Disk Built-in Caches: Evaluation on System Performance. Search on Bibsonomy MASCOTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
27Colin Atkinson 0001 Component-Oriented Verification of Software Architectures through Built-in Tests. Search on Bibsonomy ECSA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Verification, built-in tests, system services
27Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications. Search on Bibsonomy ETS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-In current sensor
27Jonathan Vincent, Graham King, Peter Lay, John Kinghorn Principles of Built-In-Test for Run-Time-Testability in Component-Based Software Systems. Search on Bibsonomy Softw. Qual. J. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF continuous test, component based software engineering, built-in-test, verification and validation
27Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee Built-in current sensor designs based on the bulk-driven technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement
27Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
27Wojciech Maly, Marek J. Patyra Design of ICs applying built-in current testing. Search on Bibsonomy J. Electron. Test. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF BIC-testing, Built-in testing, current testing
26Yavuz Kiliç, Mark Zwolinski Process variation independent built-in current sensor for analogue built-in self-test. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
25Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu Diagonal Test and Diagnostic Schemes for Flash Memorie. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF built-in self-diagnosis (BISD), memory diagnosis, built-in self-test (BIST), flash memory, memory testing, system-on-chip (SOC)
25Wei-Lun Wang, Kuen-Jong Lee Accelerated test pattern generators for mixed-mode BIST environments. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
25Der-Cheng Huang, Wen-Ben Jone An efficient parallel transparent diagnostic BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF parallel transparent diagnostic BIST, built-in self-diagnosis method, multiple embedded memory arrays, transparent diagnostic interface, redundant read/write/shift operations, march algorithm, TDiagRSMarch algorithm, low hardware overhead, test time reduction, diagnostic efficiency, parallel algorithms, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic testing, test coverage, integrated memory circuits
25Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPG for faults in system backplanes. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration
25Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits
25Christian Dufaza, Hassan Ihs A BIST-DFT technique for DC test of analog modules. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST
25Dimitrios Kagaris, Spyros Tragoudas A multiseed counter TPG with performance guarantee. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation
25T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael Faulty chip identification in a multi chip module system. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules
25Mehdi Ehsanian, Bozena Kaminska, Karim Arabi A new digital test approach for analog-to-digital converter testing. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
25Nur A. Touba, Edward J. McCluskey Applying two-pattern tests using scan-mapping. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
25Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska Design and performance of CMOS TSPC cells for high speed pseudo random testing. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
25Manoj Franklin Fast computation of C-MISR signatures. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits
25Joan Carletta, Christos A. Papachristou Testability analysis and insertion for RTL circuits based on pseudorandom BIST. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits
25Imtiaz P. Shaik, Michael L. Bushnell Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
25Javier Argüelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho Iddt testing of continuous-time filters. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF continuous time filters, continuous-time filters, design-for-test methodology, dynamic supply current consumption, dynamic current, partitioning methodology, test reliability, built-in self test, integrated circuit testing, design for testability, automatic testing, CMOS, automatic test equipment, built-in current sensor, CMOS analogue integrated circuits
25Jacob Savir On shrinking wide compressors. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers
25Joan Carletta, Christos A. Papachristou Structural constraints for circular self-test paths. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits
25Albrecht P. Stroele Signature analysis and aliasing for sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths
25Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham Efficient multisine testing of analog circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits
25Imtiaz P. Shaik, Michael L. Bushnell A graph approach to DFT hardware placement for robust delay fault BIST. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
25Laurent Leyssenne, Eric Kerherve, Yann Deval, Didier Belot A novel delta sigma built-in-current-sensor as a signal strength indicator for RF transceiver reconfiguration. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF RF power amplifier, efficiency maximization, WLAN, built-in current sensor, delta-sigma modulation
25Wimol San-Um, Masayoshi Tachibana Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test
25Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Fault-tolerance, Reliability, Testing, Built-in tests, Error-checking
25Alodeep Sanyal, Sandip Kundu A Built-in Test and Characterization Method for Circuit Marginality Related Failures. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR)
25Chen-Wei Lin, Jiun-Lang Huang A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF TFT array, charge sensing, system-on-panel, built-in self-test, LTPS
25Jiang Shi, Ricky Smith Built-In Self-Test for Embedded Voltage Regulator. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF voltage output, current loading, built-in, embedded, manufacturing, regulator, self-test
25Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-in current sensor
25Daniel Brenner, Colin Atkinson 0001, Rainer Malaka, Matthias Merdes, Barbara Paech, Dima Suliman Reducing verification effort in component-based software engineering through built-in testing. Search on Bibsonomy Inf. Syst. Frontiers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Run-time testing, MORABIT, Built-in test, Integration test
25Egas Henes Neto, Fernanda Lima Kastensmidt, Gilson I. Wirth A built-in current sensor for high speed soft errors detection robust to process and temperature variations. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF fault-tolerance, process variations, built-in current sensor
25Barend Köbben RIMapperWMS: a Web Map Service providing SVG maps with a built-in client. Search on Bibsonomy AGILE Conf. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF built-in GUI, Spatial Databases, SVG, WMS, Web Mapping
25Khoa Nguyen Tran, Zhiyong Huang Design and implementation of a built-in camera based user interface for mobile games. Search on Bibsonomy GRAPHITE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF built-in camera, user interfaces, augmented reality, mobile devices, motion detection, mobile games
25Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt Using Bulk Built-in Current Sensors to Detect Soft Errors. Search on Bibsonomy IEEE Micro The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Reliability, Built-in tests, Error-checking, Testing and Fault-Tolerance
25Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array
25Kentaroh Katoh, Hideo Ito Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. Search on Bibsonomy ETS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
25Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio An On-Chip Spectrum Analyzer for Analog Built-In Testing. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF analog IC test, built-in testing, frequency response, switched-capacitor circuits
25Yolanda Lechuga, Román Mozuelos, Miguel Angel Allende, Mar Martínez, Salvador Bracho Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF transient current test, fault detection, built-in current sensor, supply current monitoring
25Bartomeu Alorda, Sebastià A. Bota, Jaume Segura 0001 A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. Search on Bibsonomy IOLTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Current based testing, built-in current monitors, high-speed measurements, transient current
25Vishal Suthar, Shantanu Dutt High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
25Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
25Dimitri Kagaris Built-In TPG with Designed Phaseshifts. Search on Bibsonomy VTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Built-in Self-Test (BIST), Cellular Automata, Test Pattern Generation (TPG), Phase Shifters
25Taewoong Jeon, Hyonwoo Seung, Sungyoung Lee Embedding built-in tests in hot spots of an object-oriented framework. Search on Bibsonomy ACM SIGPLAN Notices The full citation details ... 2002 DBLP  DOI  BibTeX  RDF hook classes, testability, object-oriented framework, built-in test (BIT)
25Irith Pomeranz, Sudhakar M. Reddy A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF scan circuits, Built-in testing, Cartesian product
25Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test
25Yingxu Wang 0001, Graham King A European COTS Architecture with Built-in Tests. Search on Bibsonomy OOIS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF test reuse, run-time testing, Software engineering, architecture, component, COTS, built-in tests, real-time software, industrial practices, OO
25Itsuo Takanami Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF built-in selft-reconfiguration, digital neural circuit, direct spare replacement, fault-tolerance, mesh-connected processor array
25Ilker Hamzaoglu, Janak H. Patel Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
25Albrecht P. Stroele Synthesis for Arithmetic Built-In Self-Tes. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator
25Yukiya Miura, Hiroshi Yamazaki A Low-Loss Built-In Current Sensor. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF low-voltage LSIs, multiple power supplies, IDDQ testing, Built-in current sensor
25Yingxu Wang 0001, Graham King, Hakan Wickburg A Method for Built-in Tests in Component-based Software Maintenance. Search on Bibsonomy CSMR The full citation details ... 1999 DBLP  DOI  BibTeX  RDF maintenance mode, normal mode, test component reuse, reengineering maintenance, Software engineering, software maintenance, software components, built-in test
25Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy Built In Self Test for Ring Addressed FIFOs with Transparent Latches. Search on Bibsonomy MTDT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Built In Self Test, Memory testing, Embedded memories
25Christian Dufaza Multiple Paths Sensitization of Digital Oscillation Built-In Self Test. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF DOBIST, Test, Built-In Self Test
25Paul Chang, Brion L. Keller, Sarala Paliwal Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation
25Y. Tsiatouhas, Th. Haniotakis A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Built-In Self Test, Delay Fault Testing
25Yu-Yau Guo, Jien-Chung Lo Challenges of Built-In Current Sensor Designs. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF voltage regulator, built-in current sensor, Current testing, decoupling capacitor
25Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Built-in self-test, TPG, delay faults, robust testing, two-pattern tests
25O. A. Petlin, Stephen B. Furber Built-In Self-Testing of Micropipelines. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Built-in self-test, Design for test, Asynchronous design, Micropipelines
25Joseph C. W. Pang, Mike W. T. Wong, Yim-Shu Lee Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Built-in intermediate voltage sensor, bridging fault, totally self-checking circuit
25Irith Pomeranz, Sudhakar M. Reddy Built-in test generation for synchronous sequential circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF comparison units, built-in self-test, synchronous sequential circuits, at-speed test
25Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis An efficient built-in self test method for robust path delay fault testing. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF two-pattern test generator, single-input change pattern testing, robust path delay faults, built-in self test
25Josep Rius 0001, Joan Figueras Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF I DDQ testability, Built-in Current Sensors, current testing
25Marcelo Lubaszewski, Salvador Mir, Leandro Pulz ABILBO: Analog BuILt-in Block Observer. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF built-in self-test, design for test, analog and mixed-signal testing
25Albrecht P. Stroele Arithmetic Pattern Generators for Built-In Self-Test. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Arithmetic functions, built-in self-test, design for testability, pattern generator
25Stephan P. Athan, David L. Landis, Sami A. Al-Arian A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
25Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik Integration of partial scan and built-in self-test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test points, built-in self-test, design for testability, partial scan
25Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF linear hybrid cellular automata, sequential fault, transition capability, built-in self-test, linear feedback shift register, linear finite state machine
25Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis An efficient comparative concurrent Built-In Self-Test technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
23Davide Appello Session Abstract. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Probing technologies and probe cards, reduced pin count testing, multi-site efficiency, reconfigurable test resources and test resource partitioning, test generation and diagnosis, built-in and built-off DFT, test economics
23C.-Y. Kuo, J.-L. Huang A Period Tracking Based On-Chip Sinusoidal Jitter Extraction Technique. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF sinusoidal jitter, jitter decomposition, built-in self-diagnosis, built-in self-test
23Janusz Rajski, Jerzy Tyszer Recursive Pseudoexhaustive Test Pattern Generation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF recursive pseudoexhaustive test pattern generation, parallel pattern generator, exclusive-or array, serial generators, scan-based built-in self-test, logic testing, built-in self test, test vectors, characteristic functions
23John Y. Sayah, Charles R. Kime Test Scheduling in High Performance VLSI System Implementations. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF high performance VLSI system, parallel test execution, organization level, test parallelism, schedulability criteria, suboptimum heuristic-based algorithms, VLSI, built-in self-test, built-in self test, time, integrated circuit testing, design for testability, automatic testing, space, heuristic programming, test scheduling, inherent parallelism
22Dusko Karaklajic, Miroslav Knezevic, Ingrid Verbauwhede Low Cost Built in Self Test for Public Key Crypto Cores. Search on Bibsonomy FDTC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Security, Built-In Self-Test, Public-Key Cryptography, Pseudorandom Testing
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