Search results for "wafer-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar	AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	mixed-signal cores, wafer-level defect screening, packaging cost reduction, big-D/small-A mixed-signal system-on-chip designs, mixed-signal SoC, consumer electronics market, wafer-level testing, correlation-based signature analysis, low-cost digital testers, generic cost model, mixed-signal test, digital logic, test cost reduction
86	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
86	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
73	Cher Ming Tan, Kelvin Ngan Chong Yeo	A Reliability Statistics Perspective on the Pitfalls of Standard Wafer-Level Electromigration Accelerated Test (SWEAT).	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	electromigration testing, accelerated stress testing, reliability statistics, wafer-level reliability, SWEAT
67	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Wafer-Level Modular Testing of Core-Based SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
52	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Test-Pattern Ordering for Wafer-Level Test-During-Burn-In.	VTS	2008	DBLP DOI BibTeX RDF	wafer-level, pattern ordering, burn-in
49	Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, Denny Whittaker	Wafer Scale Integration: A university perspective.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
48	Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski	A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology.	ISQED	2007	DBLP DOI BibTeX RDF
48	Sule Ozev, Christian Olgaard	Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures.	VTS	2004	DBLP DOI BibTeX RDF
42	Eric Beyne	Tutorial T7A: Advanced IC Packaging.	VLSI Design	2007	DBLP DOI BibTeX RDF
37	Peter C. Maxwell	Wafer Level Reliability Screens.	ETS	2007	DBLP DOI BibTeX RDF
37	A. M. Majid, David C. Keezer, J. V. Karia	A 5 Gbps Wafer-Level Tester.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
33	Cynthia F. Murphy, Magdy S. Abadir, Peter Sandborn	Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	known good die, bare die test, multichip modules
31	William R. Mann, Frederick L. Taber, Philip W. Seitzer, Jerry J. Broz	The Leading Edge of Production Wafer Probe Test Technology.	ITC	2004	DBLP DOI BibTeX RDF
31	David L. Landis	A test methodology for wafer scale system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
30	Tz-Cheng Chiu, En-Yu Yeh	Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
30	Mesut Inac, Grzegorz Lupina, Matthias Wietstruck, Marco Lisker, Mirko Fraschke, Andreas Mai, Fabio Coccetti, Mehmet Kaynak	200 mm Wafer level graphene transfer by wafer bonding technique.	ESSDERC	2017	DBLP DOI BibTeX RDF
30	Mohamed Makhlouf, Diana Goller, Lutz Gendrisch, Stephan Kolnsberg, Franz Vogt, Alexander Utz, Dirk Weiler, Holger Vogt	Automating wafer-level test of uncooled infrared detectors using wafer-prober.	IOLTS	2017	DBLP DOI BibTeX RDF
30	Simon J. Bleiker, Maaike M. Visser Taklo, Nicolas Lietaer, Andreas Vogl, Thor Bakke, Frank Niklaus	Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding.	Micromachines	2016	DBLP DOI BibTeX RDF
30	Andreas Martin 0002, Rolf-Peter Vollertsen, A. Mitchell, M. Traving, D. Beckmeier, H. Nielen	Fast wafer level reliability monitoring as a tool to achieve automotive quality for a wafer process.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
30	Morn Jin, Wenwen He, John Qiao, Wei-Ting Kary Chien, Shirley Zhao	Wafer level package wafer probing shift error-proof quality control.	IEEM	2015	DBLP DOI BibTeX RDF
30	Sylvain Joblot, Alexis Farcy, Nicolas Hotellier, Amadine Jouve, François de Crecy, Arnaud Garnier, M. Argoud, C. Ferrandon, J.-P. Colonna, R. Franiatte, C. Laviron, Séverine Cheramy	Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration.	3DIC	2013	DBLP DOI BibTeX RDF
30	Alexander Polyakov, Marian Bartek, Joachim N. Burghartz	Mechanical Reliability of Silicon Wafers with Through-Wafer Vias for Wafer-Level Packaging.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
30	J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Wafer-level package interconnect options.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
29	Sagar S. Sabade, D. M. H. Walker	Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF	spatial correlation, IDDQ testing, delta IDDQ
28	Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz	Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs.	DATE	2008	DBLP DOI BibTeX RDF
28	Ganesh Srinivasan, Abhijit Chatterjee, Friedrich Taenzler	Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures.	VTS	2006	DBLP DOI BibTeX RDF
28	Ge Yang 0002, James A. Gaines, Bradley J. Nelson	A Supervisory Wafer-Level 3D Microassembly System for Hybrid MEMS Fabrication.	J. Intell. Robotic Syst.	2003	DBLP DOI BibTeX RDF	microgripper design, hybrid MEMS, MEMS fabrication, computer vision, microrobotics, microassembly
28	John S. Davis, David C. Keezer, Odile Liboiron-Ladouceur, Keren Bergman	Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober.	ITC	2003	DBLP DOI BibTeX RDF
28	Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O'Neill	Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation.	ITC	2002	DBLP DOI BibTeX RDF
25	Melanie Po-Leen Ooi, Ye Chow Kuang, Chris Chan, Serge N. Demidenko	Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices.	DELTA	2008	DBLP DOI BibTeX RDF	wafer testing, reliability, integrated circuits, burn-in, yield modelling
24	Annie (Yujuan) Zeng, James (JianQiang) Lü, Kenneth Rose, Ronald J. Gutmann	First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	wafer-level 3D integration, SRAM, DRAM, cache performance, Access time, cycle time
22	Erkan Acar, Sule Ozev	Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Vassilios Gerousis	Physical design implementation for 3D IC: methodology and tools.	ISPD	2010	DBLP DOI BibTeX RDF	3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv
21	Sagar S. Sabade, D. M. H. Walker	Use of Multiple IDDQ Test Metrics for Outlier Identification.	VTS	2003	DBLP DOI BibTeX RDF	Current ratio, neighbor current ratio, outlier identification, spatial correlation, IDDQ testing
21	Seongwon Jeong, Jinseok Kim 0005, Ayoung Kim, Byungwook Kim, Moonsoo Lee, Jaewon Chang, In Hak Baick, Hanbyul Kang, Younggeun Ji, Sangchul Shin, Sangwoo Pae	Optimal design of dummy ball array in wafer level package to improve board level thermal cycle reliability (BLR).	IRPS	2018	DBLP DOI BibTeX RDF
21	D. Slottke, R. J. Kamaladasa, M. Harmes, Ilan Tsameret, Mauro J. Kobrinsky, Timothy McMullen, John Dunklee	Wafer-level electromigration for reliability monitoring: Quick-turn electromigration stress with correlation to package-level stress.	IRPS	2015	DBLP DOI BibTeX RDF
21	Xiaowu Zhang, Kripesh Vaidyanathan, Tai Chong Chai, Teck Chun Tan, D. Pinjala	Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP).	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
21	Tsung-Yueh Tsai, Yi-Shao Lai, Chang-Lin Yeh, Rong-Sheng Chen	Structural design optimization for board-level drop reliability of wafer-level chip-scale packages.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
21	Alberto Fazzi, Luca Magagni, Mauro Mirandola, Barbara Charlet, Léa Di Cioccio, Erik Jung, Roberto Canegallo, Roberto Guerrieri	3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Yi-Shao Lai, Tong Hong Wang	Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
21	Detlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz	Transient-induced latch-up test setup for wafer-level and package-level.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
17	Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani	Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2024	DBLP DOI BibTeX RDF
17	Ying Gao, Xin Liu, Yanfeng Jiang	A wafer-level three-step calibration technique for BJT-based CMOS temperature sensor.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
17	Haosheng Wu, Robert Krause, Eshanee Gogoi, André Reck, Alexander Graf, Marcus Wislicenus, Olaf R. Hild, Conrad Guhl	Multielectrode Arrays at Wafer-Level for Miniaturized Sensors Applications: Electrochemical Growth of Ag/AgCl Reference Electrodes.	Sensors	2023	DBLP DOI BibTeX RDF
17		Erratum:Antenna in package design and measurement for millimeter-wave applications in fan-out wafer-level package [IEICE Electronics Express Vol. 19 (2022) No. 14 pp. 20220122].	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
17	Jiyoung Yoon, Bumgi Lee, Jaehee Song, Bokyoung Kang, Sangho Lee, Doh-Soon Kwak, Heonsang Lim, Ilsang Park, Jonghoon Kim, Sangwoo Pae	Customized wafer level verification methodology: quality risk pre-diagnosis with enhanced screen-ability of stand-by stress-related deteriorations.	IRPS	2023	DBLP DOI BibTeX RDF
17	Meindert Lunenborg, Tomasz Brozek, Laura Lorenzi, Christoph Dolainsky, Violet Liu, Xiaoyi Feng	Short-Flow Compatible Wafer-Level Reliability Assessment and Monitoring for PCM Embedded Non-Volatile Memory.	IRPS	2023	DBLP DOI BibTeX RDF
17	Ri-an Zhao, Matthew Koskinen, Yang Liu, Xinggong Wan	Voltage Ramp Stress Test Optimization for Wafer Level Hot Carrier Monitoring in FinFET.	IRPS	2023	DBLP DOI BibTeX RDF
17	Viktor Dudash, Kashi Vishwanath Machani, Bjoern Boehme, Simone Capecchi, Jungtae Ok, Karsten Meier, Frank Kuechenmeister, Marcel Wieland, Karlheinz Bock	Wafer Level Chip Scale Package Failure Mode Prediction using Finite Element Modeling.	IRPS	2023	DBLP DOI BibTeX RDF
17	Xiaojiang Liu, Gaoqiang Niu, Jin Li, Yi Zhuang, Xitong Sun, Fei Wang	MEMS Gas Sensors with Metal-Oxide Semiconductor Materials Patterned at Wafer-Level by Photolithography Technique.	SENSORS	2023	DBLP DOI BibTeX RDF
17	Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani	Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects.	ASP-DAC	2023	DBLP DOI BibTeX RDF
17	Jacob Dawes, Tzu-Hsuan Chou, Matthew L. Johnston	Lab-on-CMOS Packaging using Wafer-Level Molding and Direct-Write 3D-Printed Interconnects.	BioCAS	2023	DBLP DOI BibTeX RDF
17	Stephen Felix, Shannon Morton, Simon Stacey, John Walsh	Wafer-Level Stacking of High-Density Capacitors to Enhance the Performance of a Large Multicore Processor for Machine Learning Applications.	ISSCC	2023	DBLP DOI BibTeX RDF
17	Torben Dankwort, Minhaz Ahmed, Sven Grünzig, Anmol Khare, Björn Gojdka	High-performance Aluminum Scandium Nitride MEMS energy harvester with wafer-level integrated micromagnets for contactless rotational motion harvesting.	ICM	2023	DBLP DOI BibTeX RDF
17	Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information.	ITC	2023	DBLP DOI BibTeX RDF
17	Hao Wang 0121, Haiyang Quan, Jinqiu Zhou, Long Zhang, Jianbing Xie, Honglong Chang	A Wafer-Level Vacuum Packaged MEMS Disk Resonator Gyroscope With 0.42°/h Bias Instability Within ±300°/s Full Scale.	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
17	Simon Gassner, Rainer Schaller, Matthias Eberl, Carsten von Koblinski, Simon Essing, Mohammadamir Ghaderi, Katrin Schmitt, Jürgen Wöllenstein	Anodically Bonded Photoacoustic Transducer: An Approach towards Wafer-Level Optical Gas Sensors.	Sensors	2022	DBLP DOI BibTeX RDF
17	Zuohuan Chen, Daquan Yu, Yi Zhong	Development of 3D Wafer Level Hermetic Packaging with Through Glass Vias (TGVs) and Transient Liquid Phase Bonding Technology for RF Filter.	Sensors	2022	DBLP DOI BibTeX RDF
17	Ying Chen, Jun Li 0104, Fei Ding, Liqiang Cao	Antenna in package design and measurement for millimeter-wave applications in fan-out wafer-level package.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
17	Ping-Yi Hsieh, Artemisia Tsiara, Barry J. O'Sullivan, Didit Yudistira, Marina Baryshnikova, Guido Groeseneken, Bernardette Kunert, Marianna Pantouvaki, Joris Van Campenhout, Ingrid De Wolf	Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon.	IRPS	2022	DBLP DOI BibTeX RDF
17	Yunlong Li, Gauri Karve, Pawel E. Malinowski, Joo Hyoung Kim, Epimitheas Georgitzikis, Vladimir Pejovic, Myung-Jin Lim, Luis Moreno Hagelsieb, Renaud Puybaret, Itai Lieberman, Jiwon Lee, David Cheyns, Paul Heremans, Haris Osman, Deniz Sabuncuoglu Tezcan	Wafer Level Pixelation of Colloidal Quantum Dot Image Sensors.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
17	Teyuh Chou, Wei Tang 0010, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang	NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
17	Yusuke Saito, Yuta Ueda, Takahiko Shindo, Yu Kurata, Shigeru Kanazawa, Wataru Kobayashi, Mitsuteru Ishikawa	Vertical-Coupling Mirror Array for InP-PIC Wafer-Level Optical I/O with > 100-nm Wavelength Bandwidth.	OECC/PSC	2022	DBLP DOI BibTeX RDF
17	Michihiro Shintani, Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process.	CoRR	2021	DBLP BibTeX RDF
17	Pengfei Xu, Chaowei Si, Yurong He, Zhenyu Wei, Lu Jia, Guowei Han, Jin Ning, Fuhua Yang	A Novel High-Q Dual-Mass MEMS Tuning Fork Gyroscope Based on 3D Wafer-Level Packaging.	Sensors	2021	DBLP DOI BibTeX RDF
17	Hanxiang Zhu, Jun Li 0104, Liqiang Cao, Jia Cao, Pengwei Chen	Si-based Ka-band SIW band-pass filter using wafer level manufacturing process.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
17	Nicola Modolo, Andrea Minetto, Carlo De Santi, Luca Sayadi, Sebastien Sicre, Gerhard Prechtl, Gaudenzio Meneghesso, Enrico Zanoni, Matteo Meneghini	A Generalized Approach to Determine the Switching Reliability of GaN HEMTs on-Wafer Level.	IRPS	2021	DBLP DOI BibTeX RDF
17	Zhwen Chen, Young-Suk Kim, Tadashi Fukuda, Koji Sakui, Takayuki Ohba, Tatsuji Kobayashi, Takashi Obara	Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs.	IRPS	2021	DBLP DOI BibTeX RDF
17	Dongfang Pan, Guolong Li, Fangting Miao, Biao Deng, Junying Wei, Daquan Yu, Ming Liu, Lin Cheng 0001	A 1.25W 46.5%-Peak-Efficiency Transformer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Wafer-Level Packaging Achieving 50mW/mm2 Power Density.	ISSCC	2021	DBLP DOI BibTeX RDF
17	Yuan Liang, Chirn Chye Boon, Qian Chen 0027, Yangtao Dong	Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer.	ISCAS	2021	DBLP DOI BibTeX RDF
17	Michihiro Shintani, Riaz-ul-haque Mian, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process.	ITC	2021	DBLP DOI BibTeX RDF
17	Guoqiang Wu, Jinghui Xu, Xiaolin Zhang, Nan Wang, Danlei Yan, Jayce Lay Keng Lim, Yao Zhu, Wei Li, Yuandong Gu	Correction to "Wafer-Level Vacuum-Packaged High-Performance AlN-on-SOI Piezoelectric Resonator for Sub-100-MHz Oscillator Applications".	IEEE Trans. Ind. Electron.	2020	DBLP DOI BibTeX RDF
17	Cadmus C. A. Yuan, Chang-Chi Lee	Solder Joint Reliability Modeling by Sequential Artificial Neural Network for Glass Wafer Level Chip Scale Package.	IEEE Access	2020	DBLP DOI BibTeX RDF
17	Shunli Ma, Yan Wang, Xinyu Chen, Tianxiang Wu, Xi Wang, Hongwei Tang, Yuting Yao, Hao Yu 0001, Yaochen Sheng, Jingyi Ma, Junyan Ren, Wenzhong Bao	Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model.	IEEE Access	2020	DBLP DOI BibTeX RDF
17	Xing Quan, Jiang Luo, Guodong Su, Kai Jing, Jinsong Zhan	A Low-Loss and High-Isolation Transformer-Based mm-Wave SPDT with Integrated Fan-out Wafer Level Packaging.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
17	Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen	Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.	DATE	2020	DBLP DOI BibTeX RDF
17	Ulrich Baehr, Marvin Freier, Matthew Lewis 0003, Wolfgang Rosenstiel, Oliver Bringmann 0001	A New Method for Detecting Leaks in MEMS Accelerometers at Wafer-Level.	IEEE SENSORS	2020	DBLP DOI BibTeX RDF
17	Hayoung Lee, Donghyun Han, Hogyeong Kim, Sungho Kang 0001	W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction.	ITC-Asia	2020	DBLP DOI BibTeX RDF
17	Hardi Selg, Maksim Jenihhin, Peeter Ellervee	Wafer-Level Die Re-Test Success Prediction Using Machine Learning.	LATS	2020	DBLP DOI BibTeX RDF
17	Chen He, Yanyao Yu	Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In.	ITC	2020	DBLP DOI BibTeX RDF
17	Jaewoo Lee, Jong-Pil Im, Jeong-Hun Kim, Sol-Yee Lim, Seung-Eon Moon	Wafer-Level-Based Open-Circuit Sensitivity Model from Theoretical ALEM and Empirical OSCM Parameters for a Capacitive MEMS Acoustic Sensor.	Sensors	2019	DBLP DOI BibTeX RDF
17	Timo Schossler, Florian Schon, Christian Lemier, Gerald Urban	Wafer Level Approach for the Investigation of the Long-Term Stability of Resistive Platinum Devices at Elevated Temperatures.	IRPS	2019	DBLP DOI BibTeX RDF
17	C. S. Premachandran, Thuy Tran-Quinn, Lloyd Burrell, Patrick Justison	A Comprehensive Wafer Level Reliability Study on 65nm Silicon Interposer.	IRPS	2019	DBLP DOI BibTeX RDF
17	Constantinos Xanthopoulos, Deepika Neethirajan, Sirish Boddikurapati, Amit Nahar, Yiorgos Makris	Wafer-Level Adaptive Vmin Calibration Seed Forecasting.	DATE	2019	DBLP DOI BibTeX RDF
17	Zhongsheng Chen, Ying Zhang 0040, Zebo Peng, Jianhui Jiang	A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoC.	DATE	2019	DBLP DOI BibTeX RDF
17	Po-Chih Chen, Demin Liu, Kuan-Neng Chen	Low-Temperature Wafer-Level Metal Bonding with Gold Thin Film at 100 °C.	3DIC	2019	DBLP DOI BibTeX RDF
17	Yoshiho Maeda, Toru Miura, Shinji Matsuo, Hiroshi Fukuda	Accurate Fiber Alignment using Silicon Photodiode on Grating Coupler for Wafer-Level Testing.	OECC/PSC	2019	DBLP DOI BibTeX RDF
17	Hiroshi Fukuda, Yoshiho Maeda, Toru Miura, Shinji Matsuo	All-Optical Performance Characterization of Silicon Mach-Zehnder Modulator for Wafer-Level Test.	OECC/PSC	2019	DBLP DOI BibTeX RDF
17	Farrokh Ayazi, Haoran Wen, Yaesuk Jeong, Pranav Gupta, Anosh Daruwalla, Chang-Shun Liu	High-Q Timing and Inertial Measurement Unit Chip (TIMU) with 3D Wafer-Level Packaging.	CICC	2019	DBLP DOI BibTeX RDF
17	Tobias Gnausch, Armin Grundmann, Thomas Juhasz, Thomas Kaden, Robert Buttner, Thilo von Freyhold	Novel Opto-Electronical Probe Card for Wafer-Level PIC Testing.	OFC	2019	DBLP BibTeX RDF
17	Kuei-Cheng Lin, Po-Chang Wu, Yu-Chen Liu, Hann-Huei Tsai, Ying-Zong Juang	A 2.5D mm-size Wafer-level CMOS-IPD Wireless Power Transfer Receiver Using Cross-coupled and Self-biasing Topology for Implantable Biomedical System.	APCCAS	2019	DBLP DOI BibTeX RDF
17	Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta	Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.	DAC	2019	DBLP DOI BibTeX RDF
17	Guoqiang Wu, Jinghui Xu, Xiaolin Zhang, Nan Wang, Danlei Yan, Jayce Lay Keng Lim, Yao Zhu, Wei Li, Yuandong Gu	Wafer-Level Vacuum-Packaged High-Performance AlN-on-SOI Piezoelectric Resonator for Sub-100-MHz Oscillator Applications.	IEEE Trans. Ind. Electron.	2018	DBLP DOI BibTeX RDF
17	Mohamed Baker Alawieh, Fa Wang, Xin Li 0001	Identifying Wafer-Level Systematic Failure Patterns via Unsupervised Learning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
17	McKay Lindsay, Kevin W. Bishop, Shaan Sengupta, Megan Co, Michael Cumbie, Chien-Hua Chen, Matthew L. Johnston	Heterogeneous Integration of CMOS Sensors and Fluidic Networks Using Wafer-Level Molding.	IEEE Trans. Biomed. Circuits Syst.	2018	DBLP DOI BibTeX RDF
17	Sebastian Nessler, Maximilian Marx 0002, Yiannos Manoli	A Self-Test on Wafer Level for a MEM Gyroscope Readout Based on ΔΣ Modulation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
17	Alessandro Finocchiaro, Giovanni Girlando, Alessandro Motta, Alberto Pagani, Egidio Ragonese, Giuseppe Palmisano	Wafer-Level Contactless Testing Based on UHF RFID Tags With Post-Process On-Chip Antennas.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
17	Krishna Pradeep, Theano A. Karatsori, Thierry Poiroux, Andre Juge, Patrick Scheer, Gilles Gouget, Emmanuel Josse, Gérard Ghibaudo	Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs.	ESSDERC	2018	DBLP DOI BibTeX RDF
17	Alessandro Finocchiaro, Giovanni Girlando, Alessandro Motta, Alberto Pagani, Giuseppe Palmisano	A fully contactless wafer-level testing for UHF RFID tag with on-chip antenna.	DTIS	2018	DBLP DOI BibTeX RDF