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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5098 occurrences of 1721 keywords
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Results
Found 24872 publication records. Showing 24872 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Claudio Truzzi, Eric Beyne, Edwin Ringoot, J. Peeters |
Signal propagation in high-speed MCM circuits. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
thin film circuits, signal propagation, high-speed MCM circuits, thin-film multichip module substrate, timing analyses, lossy interconnection lines, timing, circuit analysis computing, circuit simulations, CMOS integrated circuits, CMOS integrated circuits, multichip modules, receivers, drivers, microsystems, substrates |
28 | Gert Cauwenberghs |
Bit-serial bidirectional A/D/A conversio. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process |
28 | Walter W. Weber, Adit D. Singh |
An experimental evaluation of the differential BICS for IDDQ testing. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
differential BICS, CMOS test chips, inter-layer shorts, intra-layer shorts, fault diagnosis, integrated circuit testing, fault coverage, CMOS integrated circuits, opens, built-in current sensor, IC testing, I/sub DDQ/ testing, electric current measurement, electric sensing devices |
28 | S. C. Prasad, Kaushik Roy 0001 |
Circuit optimization for minimisation of power consumption under delay constraint. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates |
28 | D. V. Poornaiah, P. V. Ananda Mohan |
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron |
28 | Rajat Subhra Chakraborty, Swarup Bhunia |
A study of asynchronous design methodology for robust CMOS-nano hybrid system design. |
ACM J. Emerg. Technol. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines |
28 | Mawahib Hussein Sulieman |
On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations. |
NanoNet |
2009 |
DBLP DOI BibTeX RDF |
Reliability, CMOS, threshold voltage, gates |
28 | Carl J. Anderson |
One look into the future of CMOS chip design. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
cmos design |
28 | Kevin Zhang 0001 |
Circuit design in nano-scale CMOS era: opportunities & challenges. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
VLSI, CMOS, circuit |
28 | Lei Zhang 0033, Zhiping Yu, Xiangqing He |
A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
CMOS Process Fluctuations, Subthreshold Current Mirror, Discrete Martingale, Probability, Random Variable |
28 | S. Yoshitomi |
Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
130 nm, RF-CMOS analog circuits, MOSFET models, EKV3.0 model, electro magnetic effects, building blocks, deep submicron |
28 | Yu Zhou, Shijo Thekkel, Swarup Bhunia |
Low power FPGA design using hybrid CMOS-NEMS approach. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
hybrid CMOS-NEMS, low power, FPGA design |
28 | Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara |
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate |
28 | Linga Reddy Cenkeramaddi, Tajeshwar Singh, Trond Ytterdal |
Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
CMUT-CMOS, analog front-end for CMUTs, charge sampling, sampling, CSA |
28 | Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas |
Modeling and estimating leakage current in series-parallel CMOS networks. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
leakage current modeling, static power dissipation, CMOS gates |
28 | Ali Bastani, Charles A. Zukowski |
Monotonic static CMOS tradeoffs in sub-100nm technologies. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
gate leakage current, monotonic static CMOS logic, low power design, noise tolerance, static power |
28 | Yarallah Koolivand, Omid Shoaei, Ali Fotowat-Ahmady, Ali Zahabi, Parviz Jabedar Maralani |
Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
CMOS LNA, cascode, inductively source degenerated (ISD), intermodulation (IM), second order interception point (IIP2), third order interception point (IIP3), volterra kernels, volterra series, linearity, distortion |
28 | Shekhar Borkar |
Electronics beyond nano-scale CMOS. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
nano, power, CMOS, variability |
28 | Shih-Chang Hsia, Wen-Ching Lee |
A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
CMOS inverter, flash, A/D converter |
28 | Saied Hemati, Amir H. Banihashemi |
Iterative decoding in analog CMOS. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
analog CMOS, analog iterative decoder, asynchronous iterative decoding, min-sum decoding, soft decoding, analog circuit, turbo codes, iterative decoding, low-density parity-check codes |
28 | Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada |
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
adiabatic logic circuit, power supply circuit, CMOS, dynamic circuit, low power circuit |
28 | Qi Wang, Sarma B. K. Vrudhula |
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
low power, CMOS circuits, dual Vt |
28 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
Lossless Transmission Lines, VLSI, Dynamic, Power, CMOS, Inductance, Short-circuit |
28 | Beyin Chen, Chung-Len Lee 0001 |
Universal test set generation for CMOS circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
functional testing, automatic test generation, CMOS circuits, stuck-open faults, universal test set |
28 | Hideki Fukuda |
Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
28 | P. C. Chen, James B. Kuo |
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | V. Kim, T. Chen |
Assessing SRAM test coverage for sub-micron CMOS technologies. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits |
27 | Chuan-Yu Wang, Kaushik Roy 0001 |
Maximum power estimation for CMOS circuits using deterministic and statistic approaches. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach |
27 | Antonio J. Acosta 0001, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas |
New CMOS VLSI linear self-timed architectures. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources |
27 | Hans Lindkvist, Per Andersson |
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders . |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic |
27 | Thomas D. Burd, Robert W. Brodersen |
Energy efficient CMOS microprocessor design. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
energy efficient CMOS microprocessor design, portable electronics, battery weight, battery size, heat dissipation, computation modes, power analysis methodology, energy efficiency quantification, computer architecture, computer architectures, throughput, parallel machines, energy consumption, energy conservation, microprocessor chips, design principles, power dissipation, CMOS digital integrated circuits, integrated circuit modelling, cooling, figures of merit, desktop computers |
27 | Abu Khari bin A'Ain, A. H. Bratt, A. P. Dorey |
Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
analogue CMOS circuits, power supply voltage control testing technique, floating gate defect exposure, power supply voltage sweep, fault diagnosis, integrated circuit testing, fault detection, fault coverage, integrated circuit modelling, CMOS analogue integrated circuits |
27 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron |
27 | Hong Hao, Edward J. McCluskey |
Analysis of Gate Oxide Shorts in CMOS Circuits. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
resistance dependence, voltage dependence, pattern dependence, logic gate operation, p-channel transistors, n-channel transistors, CMOS integrated circuits, integrated logic circuits, CMOS circuits, logic gates, defect models, temperature dependence, gate oxide shorts, semiconductor device models |
27 | Nhon T. Quach, Michael J. Flynn |
High-Speed Addition in CMOS. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit |
27 | Niraj K. Jha |
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
multiple stuck-open fault detection, logic testing, CMOS logic circuits, logic circuits, CMOS integrated circuits, integrated logic circuits, two-pattern tests |
27 | Takao Uehara, William M. van Cleemput |
Optimal Layout of CMOS Functional Arrays. |
IEEE Trans. Computers |
1981 |
DBLP DOI BibTeX RDF |
LSI layout, CMOS circuit design, CMOS functional arrays, LSI design automation, computer-aided design, design automation |
26 | Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. Likharev, Michael T. Niemier, Mingqiang Bao, Kang L. Wang |
Design and defect tolerance beyond CMOS. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
cmol, nanotechnology, defect tolerance, qca, spin wave |
26 | Suat U. Ay |
A hybrid CMOS APS pixel for wide-dynamic range imaging applications. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Konstantin Likharev |
Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Richard B. Wunderlich, Brian P. Degnan, Paul E. Hasler |
Capacitively-Biased Floating-Gate CMOS: a New Logic Family. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Jacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti |
Analysis of data dependence of leakage current in CMOS cryptographic hardware. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
leakage power consumption, side channel analysis, cryptographic hardware |
26 | Shoji Kawahito |
Circuit and Device Technologies for CMOS functional Image Sensors. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Kazuhiro Shimizu, Shinichi Hirai |
Implementing Planar Motion Tracking Algorithms on CMOS+FPGA Vision System. |
IROS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Miriam Adlerstein Marwick, Andreas G. Andreou |
Retinomorphic system design in three dimensional SOI-CMOS. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Reza M. Rad, Mohammad Tehranipoor |
A new hybrid FPGA with nanoscale clusters and CMOS routing. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
reconfigurable nanoscale devices, FPGA, molecular electronics |
26 | Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga |
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu |
BDD decomposition for mixed CMOS/PTL logic circuit synthesis. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Li Ding 0002, Pinaki Mazumder |
On circuit techniques to improve noise immunity of CMOS dynamic logic. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Yu-Chuan Shih, Chung-Yu Wu |
An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | J. Shorb, Xiaoyong Li 0001, David J. Allstot |
A resonant pad for ESD protected narrowband CMOS RF applications. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Gunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi |
High-speed add-compare-select units using locally self-resetting CMOS. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen |
Output Prediction Logic: A High-Performance CMOS Design Technique. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Niraj K. Jha |
Testing for multiple faults in domino-CMOS logic circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda |
High speed IDDQ test and its testability for process variation. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing |
24 | Eric W. MacDonald, Nur A. Touba |
Testing domino circuits in SOI technology. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits |
24 | S. L. Lin, S. Mourad, S. Krishnan |
A BIST methodology for at-speed testing of data communications transceivers. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
data communication equipment, telecommunication equipment testing, BIST methodology, data communications transceivers, data communications chip, 3-port IEEE 1394a system, CMOS implementation, 0.35 micron, 400 Mbit/s, built-in self test, integrated circuit testing, automatic testing, functional testing, CMOS integrated circuits, at-speed testing, transceivers |
24 | Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou |
etection of SRAM cell stability by lowering array supply voltage. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron |
24 | Toshiyuki Maeda, Kozo Kinoshita |
Memory reduction of IDDQ test compaction for internal and external bridging faults. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction |
24 | Zhanping Chen, Kaushik Roy 0001, Tan-Li Chou |
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
Monte Carlo based approach, maximum bounds, minimum bounds, power dissipation estimation, power sensitivity, primary inputs, signal properties, signal switching, uncertain specifications, logic CAD, CMOS logic circuits, power estimation, CMOS circuits, signal probability, statistical technique |
24 | Michael Weeks, M. B. Maaz, H. Krishnamurthy, Paul Shipley, Magdy A. Bayoumi |
A prototype chipset for a large scaleable ATM switching node. |
Great Lakes Symposium on VLSI |
1997 |
DBLP DOI BibTeX RDF |
prototype chipset, large scaleable ATM switching node, static logic, packet headers storage, dynamic logic, register file, CMOS digital integrated circuits, banyan network, CMOS IC, 1 micron |
24 | Vladimír Székely, Márta Rencz, Bernard Courtois |
Integrating on-chip temperature sensors into DfT schemes and BIST architectures. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
on-chip low-power small-area CMOS temperature sensor, DfTT, design for thermal testability, safety-critical circuit, integrated circuit testing, BIST, CMOS integrated circuits |
24 | Vishwani D. Agrawal |
Low-Power Design by Hazard Filtering. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
hazard filtering, multiple transitions, hazard pulses, differential delay, low-power design, power consumption, CMOS logic circuits, CMOS circuit, logic gate, gate delays |
24 | Minesh I. Patel, N. Ranganathan |
A VLSI System Architecture For Real-Time Intelligent Decision Making. |
ASAP |
1996 |
DBLP DOI BibTeX RDF |
VLSI system architecture, real-time intelligent decision making, backpropagation based neural network, rule based fuzzy expert system, real-time decision, CMOS VLSI chip, real-time systems, VLSI, expert systems, systolic arrays, neural nets, backpropagation, CMOS integrated circuits, adaptive learning, linear systolic arrays |
24 | Jonathan T.-Y. Chang, Edward J. McCluskey |
Quantitative analysis of very-low-voltage testing. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
very-low-voltage testing, static CMOS chips, supply voltage, rated conditions, early-life failures, test conditions, test speed, VLSI, VLSI, integrated circuit testing, CMOS integrated circuits, failure analysis, quantitative analysis, threshold voltage, integrated circuit noise |
24 | Mehdi Ehsanian, Bozena Kaminska, Karim Arabi |
A new digital test approach for analog-to-digital converter testing. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion |
24 | Diego Vázquez, José L. Huertas, Adoración Rueda |
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
sw-op amp design, CMOS implementations, design efforts, cell design, integrated circuit testing, design for testability, DFT, integrated circuit design, power dissipation, operational amplifiers, area, analogue integrated circuits, IC testing, analog integrated circuits, CMOS analogue integrated circuits |
24 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
24 | Shriram Kulkarni, Pinaki Mazumder, George I. Haddad |
A high-speed 32-bit parallel correlator for spread spectrum communication. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence |
24 | Narayanan Vijaykrishnan, N. Ranganathan |
SUBGEN: a genetic approach for subcircuit extraction. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
SUBGEN model, subcircuit extraction, large circuit graph, genetic algorithms, genetic algorithm, graph theory, computer-aided design, integrated circuit design, circuit CAD, CMOS integrated circuits, CMOS circuit, integrated circuit modelling |
24 | Sasan Iman, Massoud Pedram |
Two-level logic minimization for low power. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Power Prime Implicants, low power two-level logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets |
24 | Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang |
On Designing of 4-Valued Memory with Double-Gate TFT. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit |
24 | Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai |
A prototype router for the massively parallel computer RWC-1. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
prototype router, massively parallel computer RWC-1, multi-threaded architecture, high communication performance, direct interconnection networks, small degree, operating system support features, CMOS gate array, VLSI, parallel architectures, multiprocessor interconnection networks, CMOS integrated circuits, high throughput, low latency, hardware cost, VLSI chip |
24 | Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan |
PEPPER - a timing driven early floorplanner. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay |
24 | Kenneth Y. Yun, David L. Dill |
A high-performance asynchronous SCSI controller. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
peripheral interfaces, high-performance asynchronous SCSI controller, small computer systems interface, asynchronous pipeline, extended burst-mode machines, CMOS standard cell, data transfer throughput, distributed control scheme, extended burst-mode state machines, synchronisation, distributed control, CMOS integrated circuits, FIFO |
24 | Hosahalli R. Srinivas, Keshab K. Parhi |
A floating point radix 2 shared division/square root chip. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
floating point radix 2 shared division/square root chip, full-custom 1.2 micron CMOS VLSI chip, single precision IEEE 754 std. floating point numbers, square root algorithm, digit-by-digit schemes, quotient/root digit selection, 5.0 V, 66 MHz, VLSI, floating point arithmetic, CMOS integrated circuits, IEEE standards, dividing circuits, 1.2 micron, division algorithm |
24 | Mark R. Greenstreet |
Implementing a STARI chip. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits |
24 | Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto |
A 13.3ns double-precision floating-point ALU and multiplier. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit |
24 | Kei-Yong Khoo, Alan N. Willson Jr. |
Single-transistor transparent-latch clocking. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits |
24 | Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth |
Analog VLSI circuits for manufacturing inspection. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits |
24 | N. Ranganathan, K. B. Doreswamy |
A systolic algorithm and architecture for image thinning. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects |
24 | Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan |
Circuit/architecture for low-power high-performance 32-bit adder. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit |
24 | Aditya Agrawal, Anand Raju, Sachidanand Varadarajan, Magdy A. Bayoumi |
A scalable shared buffer ATM switch architecture. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access |
24 | Jae-Tack Yoo, Erik Brunvand, Kent F. Smith |
Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC |
24 | S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta |
A single chip, pipelined, cascadable, multichannel, signal processor. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron |
24 | Vincenzo Catania, Marco Russo |
Analog gates for a VLSI fuzzy processor. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
VLSI fuzzy processor, synchronous fuzzy circuits, high noise immunity, fuzzy gates, VLSI, fuzzy logic, CMOS logic circuits, CMOS technology, logic gates, analogue processing circuits |
24 | Ali Skaf, Alain Guyot |
SAGA: the first general-purpose on-line arithmetic co-processor. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
general-purpose co-processor, online arithmetic coprocessor, VLSI realisation, BKM algorithm, complex logarithm function, complex exponential function, VLSI, arithmetic, coprocessors, CMOS digital integrated circuits, redundant number systems, CMOS IC, SAGA |
24 | Mario Kovac, N. Ranganathan |
JAGUAR: a high speed VLSI chip for JPEG image compression standard. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz |
24 | Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky |
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform |
24 | Ru Huang, HanMing Wu, Jinfeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, Runsheng Wang, Liangliang Zhang, Xing Zhang 0002, Yangyuan Wang |
Challenges of 22 nm and beyond CMOS technology. |
Sci. China Ser. F Inf. Sci. |
2009 |
DBLP DOI BibTeX RDF |
22 nm technology node, device architectures, metal gate/high K dielectrics, ultra low K dielectrics, CMOS technology |
24 | Sergio Chaparro, Armando Ayala Pabón, Elkim Roa, Wilhelmus A. M. Van Noije |
A merged RF CMOS LNA-Mixer design using geometric programming. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
LNA-Mixer, RF-CMOS inductors, optimization, analog circuits, geometric programming |
24 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design |
24 | Yarallah Koolivand, Seyed Morteza Alavi, Omid Shoaei |
New technique in design of active rf cmos mixers for low flicker noise and high conversion gain. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
1.cmos mixer, direct conversion receiver, flicker noise, sub-threshold, ota, noise figure |
24 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman |
Full Open Defects in Nanometric CMOS. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
interconnect open, gate leakage current, CMOS |
24 | Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia |
Viability of analog inner product operations in CMOS imagers. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
CMOS analog hardware, analog image processing, vector quantization |
24 | Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider |
A comparative study of CMOS gates with minimum transistor stacks. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates |
24 | Fernando de Souza Campos, Ognian Marinov, Naser Faramarzpour, Fayçal Saffih, M. Jamal Deen, Jacobus W. Swart |
A multisampling time-domain CMOS imager with synchronous readout circuit. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
fill-factor, dynamic range, CMOS imager, active pixel sensor |
24 | Cosmin Popa |
Linearized CMOS active resistor independent on the bulk effect. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
CMOS design, active resistor, linearity, area minimization |
24 | Luis Henrique de Carvalho Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. M. Van Noije |
Ultra low-voltage ultra low-power CMOS threshold voltage reference. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
low power, CMOS, low voltage, threshold voltage, voltage reference |
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