Search results for "high-k"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	David Wolpert 0001, Paul Ampadu	Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates.	NanoNet	2008	DBLP DOI BibTeX RDF	Reverse temperature dependence, high-k dielectric, variation-tolerant, metal gate
10	A. Madan, S. C. Bose, P. J. George, Chandra Shekhar 0001	Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs.	VLSI Design	2005	DBLP DOI BibTeX RDF	Direct Tunneling, gate leakage current, high-K gate stack, MOSFETs
9	Joseph Casamento, Kazuki Nomoto, Thai-Son Nguyen, Hyunjea Lee, Chandrasekhar Savant, Lei Li 0023, Austin Hickman, Takuya Maeda, Yu-Tsun Shao, Jimy Encomendero, Ved Gund, Timothy Vasen, Shamima Afroz, Daniel J. Hannan, David A. Muller, Huili Grace Xing, Debdeep Jena	AlScN High Electron Mobility Transistors: Integrating High Piezoelectric, High K Dielectric, and Ferroelectric Functionality.	BCICTS	2023	DBLP DOI BibTeX RDF
8	Ru Huang, HanMing Wu, Jinfeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, Runsheng Wang, Liangliang Zhang, Xing Zhang 0002, Yangyuan Wang	Challenges of 22 nm and beyond CMOS technology.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	22 nm technology node, device architectures, metal gate/high K dielectrics, ultra low K dielectrics, CMOS technology
8	Yangyuan Wang, Xing Zhang 0002, Xiaoyan Liu, Ru Huang	Novel devices and process for 32 nm CMOS technology and beyond.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	high-k, non-planar MOSFET, quasi-ballistic transport, CMOS technology, metal gate
7	Kelin J. Kuhn	CMOS scaling beyond 32nm: challenges and opportunities.	DAC	2009	DBLP DOI BibTeX RDF	high-k, CMOS, orientation, strain, metal-gate
6	Samar K. Saha	Modeling Process Variability in Scaled CMOS Technology.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	compact variability modeling, gate-oxide thickness variability, high-k dielectric, line-edge roughness, polysilicon granularity, random discrete dopants, scaled CMOS technology, statistical compact modeling, design and test, process variability, metal gate
6	Tae-Hwan Hyun, Won-Ju Cho	Pushing the Limits of Biosensing: Selective Calcium Ion Detection with High Sensitivity via High-k Gate Dielectric Engineered Si Nanowire Random Network Channel Dual-Gate Field-Effect Transistors.	Sensors	2023	DBLP DOI BibTeX RDF
6	Kamal Hosen, Md. Sherajul Islam, Catherine Stampfl, Jeongwon Park	Numerical Analysis of Gate-All-Around HfO2/TiO2/HfO2 High-K Dielectric Based WSe2 NCFET With Reduced Sub-Threshold Swing and High On/Off Ratio.	IEEE Access	2021	DBLP DOI BibTeX RDF
6	Shaun Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, Philex Fan, Chia-En Huang, Yu-Der Chih, Yih Wang, Jonathan Chang	A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
6	Yutao Cai, Yang Wang, Ye Liang, Yuanlei Zhang, Wen Liu 0010, Huiqing Wen, Ivona Z. Mitrovic, Cezhou Zhao	Effect of High-k Passivation Layer on High Voltage Properties of GaN Metal-Insulator-Semiconductor Devices.	IEEE Access	2020	DBLP DOI BibTeX RDF
6	Jing-Chyi Liao, Paul Ko, M. H. Hsieh, Zheng Zeng	Self-healing LDMOSFET for high-voltage application on high-k/metal gate CMOS process.	IRPS	2020	DBLP DOI BibTeX RDF
6	Deepa Anand, M. Swathi, A. Purushothaman, Sundararaman Gopalan	Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate.	ICACDS (1)	2018	DBLP DOI BibTeX RDF
6	Shweta Shree, Umesh Chandra Pancholi	Fabrication and study of various characteristics of high performance iii-v mosfets with high-k dielectrics.	ICACCI	2017	DBLP DOI BibTeX RDF
6	Sheng-Po Fang, Kyoung-Tae Kim, Todd Schumann, Yong-Kyu Yoon	Fabrication of high-aspect-ratio nanoporous high-k MTiO3 (M= Ba, Sr, or BaxSr1-x) using anodization and hydrothermal processes.	NEMS	2017	DBLP DOI BibTeX RDF
6	A. Benoist, S. Denorme, X. Federspiel, Bruno Allard, Philippe Candelier	Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology.	IRPS	2015	DBLP DOI BibTeX RDF
6	Jungyul Pyo, Youngmin Shin, Hoi-Jin Lee, Sung-il Bae, Min-Su Kim, Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-Wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chunghee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Ukrae Cho, Jae Cheol Son, Sungho Park	23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor.	ISSCC	2015	DBLP DOI BibTeX RDF
6	S. H. Yang, J. Y. Sheu, M. K. Ieong, M. H. Chiang, T. Yamamoto, J. J. Liaw, S. S. Chang, Y. M. Lin, T. L. Hsu, J. R. Hwang, J. K. Ting, C. H. Wu, K. C. Ting, F. C. Yang, C. M. Liu, I. L. Wu, Y. M. Chen, S. J. Chent, K. S. Chen, J. Y. Cheng, M. H. Tsai, W. Chang, R. Chen, C. C. Chen, T. L. Lee, C. K. Lin, S. C. Yang, Y. M. Sheu, J. T. Tzeng, L. C. Lu, S. M. Jang, Carlos H. Diaz, Yuh-Jier Mii	28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications.	CICC	2011	DBLP DOI BibTeX RDF
6	W. Polspoel, Wilfried Vandervorst, Lidia Aguilera, Marc Porti, Montserrat Nafría, Xavier Aymerich	Nanometer-scale leakage measurements in high vacuum on de-processed high-k capacitors.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
6	Y. H. Kim, Rino Choi, R. Jha, J. H. Lee, Veena Misra, J. C. Lee	Reliability of High-K Dielectrics and Its Dependence on Gate Electrode and Interfacial / High-K Bi-Layer Structure.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
5	Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao	Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.	VLSI Design	2003	DBLP DOI BibTeX RDF
5	Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao	Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.	VLSI Design	2001	DBLP DOI BibTeX RDF
4	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
4	Chenyue Ma, Bo Li, Lining Zhang, Jin He 0003, Xing Zhang 0002, Xinnan Lin, Mansun Chan	A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability.	ISQED	2009	DBLP DOI BibTeX RDF
4	D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao	Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
3	Lijuan Wu, Tao Qiu, Xuanting Song, Banghui Zhang, Heng Liu, Qing Liu	Analytical model for high-k SOI pLDMOS with self-adaptive balance of polarization charge.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
3	X. Federspiel, A. Griffon, M. Barlas, P. Lamontagne	Effect of Frequency on Reliability Of High-K MIM Capacitors.	IRPS	2023	DBLP DOI BibTeX RDF
3	Shraddha Pali, Ankur Gupta	High-k field plate DeNMOS design for enhanced performance and electrothermal SOA in switching applications.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
3	Ravi Achanta, V. McGahay, S. Boffoli, C. Kothandaraman, J. Gambino	High-k MIM dielectric reliability study in 65nm node.	IRPS	2022	DBLP DOI BibTeX RDF
3	Yiming Qu, Yang Shen, Mingji Su, Jiwu Lu, Yi Zhao	GHz C-V Characterization Methodology and Its Application for Understanding Polarization Behaviors in High-k Dielectric Films.	IRPS	2022	DBLP DOI BibTeX RDF
3	Chih-Feng Yen, Yu-Ya Huang, Shen-Hao Tsao, Shih-Hao Lin, Chun-Hu Cheng	Influence of Y2O3 Doped HfO2 High-k Films on Electrical Properties of MOS and MIM Devices.	ICKII	2022	DBLP DOI BibTeX RDF
3	L. Breuil, L. Nyns, S. Rachidi, K. Banerjee, Antonio Arreghini, J. Bastos, S. Ramesh, G. Van den Bosch, Maarten Rosmeulen	High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction.	IMW	2022	DBLP DOI BibTeX RDF
3	Vishank Talesara, Yuxuan Zhang, Junao Cheng, Hongping Zhao, Wu Lu	Breakdown Voltage Enhancement of GaN diodes with High-k Dielectric.	DRC	2022	DBLP DOI BibTeX RDF
3	Ana Ruiz, Carlos Couso, Natalia Seoane, Marc Porti, Antonio J. García-Loureiro, Montserrat Nafría	Methodology for the Simulation of the Variability of MOSFETs With Polycrystalline High-k Dielectrics Using CAFM Input Data.	IEEE Access	2021	DBLP DOI BibTeX RDF
3	Sarika Madhukar Jagtap, Vitthal Janardan Gond	Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics.	Int. J. Nat. Comput. Res.	2021	DBLP DOI BibTeX RDF
3	Bingfei Dou, Siwei Huang, Jiajin Song, Xiao Li, Zongming Duan, Xiaojiang Yao, Dongping Xiao, Yongjie Li 0002, Liguo Sun	A 21.6dBm CMOS power amplifier using a compact high-k output transformer for X-band application.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
3	Konner E. K. Holden, Gavin D. R. Hall, Michael Cook 0004, Chris Kendrick, Kaitlyn Pabst, Bruce Greenwood, Robin Daugherty, Jeff P. Gambino, Derryl D. J. Allman	Dielectric Relaxation, Aging and Recovery in High-K MIM Capacitors.	IRPS	2021	DBLP DOI BibTeX RDF
3	Hongxia Liu, Guodu Han, Dong Wang	Research on Transparent Resistive Random Memory Based on Lanthanum-based High-k Medium.	ASICON	2021	DBLP DOI BibTeX RDF
3	Rui Li, Mingmin Huang, Xi Zhang, Min Hu, Zhimei Yang, Yao Ma, Min Gong	Superjunction MOSFET with Trench Schottky Contact and Embedded High-k Insulator for Excellent Reverse Recovery.	ASICON	2021	DBLP DOI BibTeX RDF
3	Pooja Srivastava, S. C. Bose	Simulated Analysis of Double-Gate MOSFET and FinFET Structure Using High-k Materials.	COMS2	2021	DBLP DOI BibTeX RDF
3	Walid Amir, Dae-Hyun Kim, Tae-Woo Kim	Comprehensive Analysis of Quantum Mechanical Effects of Interface Trap and Border Trap Densities of High-k Al2O3/In0.53Ga0.47As on a 300-mm Si Substrate.	IEEE Access	2020	DBLP DOI BibTeX RDF
3	Aakash Kumar Jain, Mamidala Jagadesh Kumar	Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study.	IEEE Access	2020	DBLP DOI BibTeX RDF
3	Junji Cheng, Jingjie Lin, Weizhen Chen, Shiying Wu, Haimeng Huang, Bo Yi	Lateral Power Fin MOSFET With a High-k Passivation for Ultra-Low On-Resistance.	IEEE Access	2020	DBLP DOI BibTeX RDF
3	Saurav Roy, Arkka Bhattacharyya, Sriram Krishnamoorthy	Analytical Modeling and Design of Gallium Oxide Schottky Barrier Diodes Beyond Unipolar Figure of Merit Using High-k Dielectric Superjunction Structures.	CoRR	2020	DBLP BibTeX RDF
3	Shun'ichiro Ohmi, Shin Ishimatsu, Yuske Horiuchi, Sohya Kudoh	In-Situ N2-Plasma Nitridation for High-k HfN Gate Insulator Formed by Electron Cyclotron Resonance Plasma Sputtering.	IEICE Trans. Electron.	2020	DBLP DOI BibTeX RDF
3	Ygor Fonseca, Rafael Nóbrega, Ulysses Duarte, Thiago R. Raddo, Iyad Dayoub, Anderson L. Sanches, Murilo Bellezoni Loiola	Analysis of Si and GaN GAA-NW-FETs in High-k Gate Oxides for Next Generation Mobile Systems.	CSNDSP	2020	DBLP DOI BibTeX RDF
3	Ying-Jun Deng, Hao-Lun Hu, Yu-Han Liang, Jian-Ming Chen, Ching-Chuan Chou, Shea-Jue Wang, Mu-Chun Wang	Q-factor Integrity of 28nm-node High-k Gate Dielectric.	ICKII	2020	DBLP DOI BibTeX RDF
3	Yu-Chen Lin, Kai-Chun Zhan, Ji-Min Zhang, Jian-Ming Chen, Cheng-Hsun-Tony Chang, Shea-Jue Wang, Mu-Chun Wang	Junction Integrity for 28nm High-k nMOSFETs with Thermal Stress.	ICKII	2020	DBLP DOI BibTeX RDF
3	Si-Ping Li, Jia-Wei Xu, Wei-Hao Li, Jian-Ming Chen, Chao-Nan Wei, Wen-How Lan, Mu-Chun Wang	Patterns of Exposing Integrity of 28nm-node High-k Gate Dielectric on p-substrate with Nitridation Treatments.	ICKII	2020	DBLP DOI BibTeX RDF
3	Kyung Eun Park, Shun'ichiro Ohmi	High-k LaBxNy gate insulator formed by the Ar/N2 plasma sputtering of N-doped LaB6 metal thin films and its application to floating-gate memory.	DRC	2020	DBLP DOI BibTeX RDF
3	Akanksha Rohit, Yunus Kelestemur, Savas Kaya, Parthiban Rajan	Ultra-Durable and Reliable High-k Textile Capacitors for Wearables and Robotics.	DRC	2020	DBLP DOI BibTeX RDF
3	Swarnil Roy, Sagar Mukherjee, Arka Dutta, Chandan Kumar Sarkar, Chayanika Bose	Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
3	Avtar Singh, Saurabh Chaudhury, Chandan Kumar Pandey, Savitesh Madhulika Sharma, Chandan Kumar Sarkar	Design and analysis of high k silicon nanotube tunnel FET device.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
3	Wei-feng Lü, Liang Dai	Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
3	Chandreswar Mahata, Wonwoo Kim, Shiwhan Kim, Muhammad Ismail, Min-Hwi Kim, Sungjun Kim, Byung-Gook Park	Reversible nonvolatile and threshold switching characteristics in Cu/high-k/Si devices.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
3	Yueyang Liu, Xiangwei Jiang, Liwei Wang 0003, Yunfei En, Runsheng Wang	Distinguishing Interfacial Hole Traps in (110), (100) High-K Gate Stack.	IRPS	2019	DBLP DOI BibTeX RDF
3	E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung	The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
3	Yutao Cai, Yang Wang, Miao Cui, Wen Liu 0010, Huiqing Wen, Cezhou Zhao, Ivona Z. Mitrovic, Stephen Taylor, Paul R. Chalker	Effect of High-k Passivation Layer on Electrical Properties of GaN Metal-Insulator-Semiconductor Devices.	ICICDT	2019	DBLP DOI BibTeX RDF
3	Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz Gardner, Seung-Hoon Sung, Paul Fischer	High-K Gate Dielectric GaN MOS-HEMTs with Regrown n+ InGaN Source/Drain (Invited Paper).	DRC	2019	DBLP DOI BibTeX RDF
3	Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer	80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
3	Rajneesh Sharma, Rituraj S. Rathore, Ashwani K. Rana	Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
3	Minjung Jin, Kangjung Kim, Yoohwan Kim, Hyewon Shim, Jinju Kim, Gunrae Kim, Sangwoo Pae	Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
3	Jiangwei Liu, Yasuo Koide	An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors.	Sensors	2018	DBLP DOI BibTeX RDF
3	Nicolo Oliva, Emanuele A. Casu, Matteo Cavalleri, Adrian M. Ionescu	Double gate n-type WSe2 FETs with high-k top gate dielectric and enhanced electrostatic control.	ESSDERC	2018	DBLP DOI BibTeX RDF
3	Badreddine Zerroumda, Fayçal Djeffal, Toufik Bentrcia, Hichem Ferhati	Numerical Analysis of 4H-SiC MOSFET Design Including High-k Gate Dielectrics for Power electronic Applications.	ICSENT	2018	DBLP DOI BibTeX RDF
3	D. S. Huang, J. H. Lee, Y. S. Tsai, Y. F. Wang, Y. S. Huang, C. K. Lin, Ryan Lu, Jun He	Comprehensive device and product level reliability studies on advanced CMOS technologies featuring 7nm high-k metal gate FinFET transistors.	IRPS	2018	DBLP DOI BibTeX RDF
3	Weizhen Chen, Junji Cheng, Jingjie Lin, Xingbi Chen	Simulation study on the high-k SJ-VDMOS with gradient side-wall.	MIPRO	2018	DBLP DOI BibTeX RDF
3	Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata	14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
3	Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang	0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process.	SoCC	2018	DBLP DOI BibTeX RDF
3	Anna Grazia Monteduro, Zoobia Ameer, Silvia Rizzato, Angelo Leo, Maurizio Martino, Anna Paola Caricato, Vittorianna Tasco, Indira Chaitanya Lekshmi, Abhijit Hazarika, Debraj Choudhury, Elisabetta Mazzotta, Cosimino Malitesta, D. D. Sarma, Giuseppe Maruccio	High-k YCTO thin films for electronics.	ICICDT	2018	DBLP DOI BibTeX RDF
3	Jeffrey A. Smith, Hideki Takeuchi, Robert Stephenson, Yi-Ann Chen, Marek Hytha, Robert J. Mears, Suman Datta	Experimental Investigation of N-Channel Oxygen-Inserted (OI) Silicon Channel MOSFETs with High-K/Metal Gate Stack.	DRC	2018	DBLP DOI BibTeX RDF
3	Namphung Peimyoo, Jake Mehew, Matt D. Barnes, Adolfo De Sanctis, Iddo Amit, Janire Escolar, Konstantinos Anastasiou, Ali Gholina, Aidan P. Rooney, Sarah Haigh, Saverio Russo, Monica Felicia Craciun, Freddie Withers	Photo-oxidized HfS2 - An embeddable and writable high-k dielectric for flexible Van der Waals nano-electronics.	DRC	2018	DBLP DOI BibTeX RDF
3	Shimpei Yamaguchi, Zeynel Bayindir, Xiaoli He, Suresh Uppal, Purushothaman Srinivasan, Chloe Yong, Dongil Choi, Manoj Joshi, Hyuck Soo Yang, Owen Hu, Srikanth Samavedam, Dong Kyun Sohn	Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
3	Slah Hlali, Neila Hizem, Liviu Militaru, A. Kalboussi, Abdelkader Souifi	Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
3	Mengnan Ke, Mitsuru Takenaka, Shinichi Takagi	Understanding of slow traps generation in plasma oxidation GeOx/Ge MOS interfaces with ALD high-k layers.	ESSDERC	2017	DBLP DOI BibTeX RDF
3	Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu	12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.	ISSCC	2017	DBLP DOI BibTeX RDF
3	D. H. Triyoso, G. R. Mulfinger, K. Hempel, H. Tao, F. Koehler, L. Kang, A. Kumar, T. McArdle, J. Holt, A. L. Child, S. Straub, F. Ludwig, Z. Chen, J. Kluth, Rick Carter	Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor.	ICICDT	2017	DBLP DOI BibTeX RDF
3	Kai-Ping Chang, Han-Hsiang Tai, Jer-Chyi Wang, Chao-Sung Lai	Graphene nanodots with high-k dielectrics for flash memory applications.	ASICON	2017	DBLP DOI BibTeX RDF
3	Tilo Köckritz, René Luther, Georgi Paschew, Irene Jansen, Andreas Richter, Oliver Jost, Andreas Schönecker, Eckhard Beyer	Full Polymer Dielectric Elastomeric Actuators (DEA) Functionalised with Carbon Nanotubes and High-K Ceramics.	Micromachines	2016	DBLP DOI BibTeX RDF
3	Sanjit Kumar Swain, Arka Dutta, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar	Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
3	Feng Ji, Jing-Ping Xu, Lu Liu, Wing Man Tang, Pui To Lai	A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
3	Andreas Kerber	Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
3	Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer	80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
3	Bo Song, Jianliang Gao, Weimao Ke, Xiaohua Hu 0001	Achieving high k-coverage and k-consistency in global alignment of multiple PPI networks.	BIBM	2016	DBLP DOI BibTeX RDF
3	Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav, Santosh Kumar Vishvakarma	Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter.	iNIS	2016	DBLP DOI BibTeX RDF
3	Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma	Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET.	iNIS	2016	DBLP DOI BibTeX RDF
3	Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori	A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
3	Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, Chris H. Kim	A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
3	Binola K. Jebalin, A. Shobha Rekh, P. Prajoon, N. Mohankumar 0002, D. Nirmal	The influence of high-k passivation layer on breakdown voltage of Schottky AlGaN/GaN HEMTs.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
3	K. C. Lin, P. C. Juan, C. H. Liu, Mu-Chun Wang, C. H. Chou	Leakage current mechanism and effect of Y2O3 doped with Zr high-K gate dielectrics.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
3	Hsien-Chin Chiu, Chia-Hsuan Wu, Ji-Fan Chi, Jen-Inn Chyi, Geng-Yen Lee	N2O treatment enhancement-mode InAlN/GaN HEMTs with HfZrO2 High-k insulator.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
3	Mattia Capriotti, Clément Fleury, Ole Bethge, Matteo Rigato, Suzanne Lancaster, Dionyz Pogany, Gottfried Strasser, Eldad Bahat-Treidel, Oliver Hilt, Frank Brunner, Joachim Würfl	E-mode AlGaN/GaN True-MOS, with high-k ZrO2 gate insulator.	ESSDERC	2015	DBLP DOI BibTeX RDF
3	M. N. Chang, Y.-H. Lee, S. Y. Lee, C. C. Chiu, D. Maji, K. Wu	An investigation of capacitance aging model for extreme low-k and high-k dielectrics.	IRPS	2015	DBLP DOI BibTeX RDF
3	P. Srinivasan, J. Fronheiser, S. Siddiqui, A. Kerber, L. F. Edge, Richard G. Southwick, Eduard Cartier	NBTI in Si0.5Ge0.5 RMG gate stacks - Effect of high-k nitridation.	IRPS	2015	DBLP DOI BibTeX RDF
3	A. Kerber	Impact of RTN on stochastic BTI degradation in scaled metal gate/high-k CMOS technologies.	IRPS	2015	DBLP DOI BibTeX RDF
3	A. Bezza, M. Rafik, David Roy 0001, X. Federspiel, P. Mora, Cheikh Diouf, Vincent Huard, Gérard Ghibaudo	Physical understanding of low frequency degradation of NMOS TDDB in High-k metal gate stack-based technology. Implication on lifetime assessment.	IRPS	2015	DBLP DOI BibTeX RDF
3	G. Sereni, Luca Vandelli, Roberto Cavicchioli, Luca Larcher, Dmitry Veksler, Gennadi Bersuker	Substrate and temperature influence on the trap density distribution in high-k III-V MOSFETs.	IRPS	2015	DBLP DOI BibTeX RDF
3	Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De	Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS.	CICC	2015	DBLP DOI BibTeX RDF
3	Kanchan Cecil, Jawar Singh	Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k.	iNIS	2015	DBLP DOI BibTeX RDF
3	Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla	Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high-K spacers.	GCCE	2015	DBLP DOI BibTeX RDF