Search results for "metal-gate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra	A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.	ISQED	2009	DBLP DOI BibTeX RDF
66	Hamed F. Dadgour, Vivek De, Kaustav Banerjee	Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design.	ICCAD	2008	DBLP DOI BibTeX RDF
61	Yangyuan Wang, Xing Zhang 0002, Xiaoyan Liu, Ru Huang	Novel devices and process for 32 nm CMOS technology and beyond.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	high-k, non-planar MOSFET, quasi-ballistic transport, CMOS technology, metal gate
44	Kelin J. Kuhn	CMOS scaling beyond 32nm: challenges and opportunities.	DAC	2009	DBLP DOI BibTeX RDF	high-k, CMOS, orientation, strain, metal-gate
44	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
41	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy 0001	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
40	Ru Huang, HanMing Wu, Jinfeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, Runsheng Wang, Liangliang Zhang, Xing Zhang 0002, Yangyuan Wang	Challenges of 22 nm and beyond CMOS technology.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	22 nm technology node, device architectures, metal gate/high K dielectrics, ultra low K dielectrics, CMOS technology
38	Santosh Kumar Gupta, Srimanta Baishya	On the analog and radio frequency performance of Junctionless Single Metal Gate cylindrical surround gate metal-oxide-semiconductor field-effect transistors.	Simul.	2014	DBLP DOI BibTeX RDF
32	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001	Modeling and Analysis of Leakage Currents in Double-Gate Technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
32	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.	ISLPED	2005	DBLP DOI BibTeX RDF	double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage
29	Mohamed T. Ghoneim, Jhonathan P. Rojas, Chadwin D. Young, Gennadi Bersuker, Muhammad Mustafa Hussain	Electrical Analysis of High Dielectric Constant Insulator and Metal Gate Metal Oxide Semiconductor Capacitors on Flexible Bulk Mono-Crystalline Silicon.	IEEE Trans. Reliab.	2015	DBLP DOI BibTeX RDF
29	Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer 0002, Bernd Becker 0001, Subhasish Mitra	Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.	CICC	2013	DBLP DOI BibTeX RDF
29	Saraju P. Mohanty, Elias Kougianos	Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-κ/metal-gate nano-complementary metal-oxide semiconductor static random access memory.	IET Comput. Digit. Tech.	2012	DBLP DOI BibTeX RDF
29	Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang 0013, Brian Pedersen, Kevin Zhang 0001	A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
29	Chel-Jong Choi, Ha-Yong Yang, Hyo-Bong Hong, Jin-Gyu Kim, Sung-Yong Chang, Jouhahn Lee	Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
28	Samar K. Saha	Modeling Process Variability in Scaled CMOS Technology.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	compact variability modeling, gate-oxide thickness variability, high-k dielectric, line-edge roughness, polysilicon granularity, random discrete dopants, scaled CMOS technology, statistical compact modeling, design and test, process variability, metal gate
28	David Wolpert 0001, Paul Ampadu	Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates.	NanoNet	2008	DBLP DOI BibTeX RDF	Reverse temperature dependence, high-k dielectric, variation-tolerant, metal gate
28	Wei-feng Lü, Liang Dai	Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
28	Barry J. O'Sullivan, Romain Ritzenthaler, Gerhard Rzepa, Z. Wu, E. Dentoni Litta, O. Richard, T. Conard, V. Machkaoutsan, Pierre Fazan, C. Kim, Jacopo Franco, Ben Kaczer, Tibor Grasser, Alessio Spessot, Dimitri Linten, N. Horiguchi	Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.	IRPS	2019	DBLP DOI BibTeX RDF
28	E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung	The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
28	Minjung Jin, Kangjung Kim, Yoohwan Kim, Hyewon Shim, Jinju Kim, Gunrae Kim, Sangwoo Pae	Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
28	Wei-feng Lü, Mi Lin, Haipeng Zhang	Investigation on Gate Capacitances Fluctuation Due to Work-Function Variation in Metal-Gate FinFETs.	FSDM	2017	DBLP DOI BibTeX RDF
28	Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De	Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS.	CICC	2015	DBLP DOI BibTeX RDF
28	Dongwoo Kim 0002, Seonhaeng Lee, Cheolgyu Kim, Chiho Lee, Jeongsoo Park 0005, Bongkoo Kang	Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under channel hot-carrier/gate-induced drain leakage alternating stress.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
28	Romain Ritzenthaler, Tom Schram, Erik Bury, Jérôme Mitard, L.-Å. Ragnarsson, Guido Groeseneken, N. Horiguchi, Aaron Thean, Alessio Spessot, Christian Caillat, V. Srividya, Pierre Fazan	Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.	ESSDERC	2012	DBLP DOI BibTeX RDF
28	Dick James	Intel Ivy Bridge unveiled - The first commercial tri-gate, high-k, metal-gate CPU.	CICC	2012	DBLP DOI BibTeX RDF
28	D. H. Triyoso, V. Jaschke, Jeff Shu, S. Mutas, Klaus Hempel, Jamie K. Schaeffer, Markus Lenski	Robust PEALD SiN spacer for gate first high-k metal gate integration.	ICICDT	2012	DBLP DOI BibTeX RDF
28	Takuya Imamoto, Takeshi Sasaki, Tetsuo Endoh	Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65 nm CMOS Process.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
28	Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta	Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
28	Jing-Ping Xu, X. Xiao, Pui-To Lai	A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
28	Ralf Endres, Yordan Stefanov, Udo Schwalke	Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
28	S. Chatterjee, Yue Kuo, J. Lu, J.-Y. Tewg, P. Majhi	Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
28	Takeo Matsuki, Kazuyoshi Torii, Takeshi Maeda, Yasushi Akasaka, Kiyoshi Hayashi, Naoki Kasai, Tsunetoshi Arikado	Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
28	S. Beckx, M. Demand, S. Locorotondo, K. Henson, M. Claes, V. Paraschiv, D. Shamiryan, P. Jaenen, W. Boullart, S. Degendt	Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
28	Takayuki Yamada, Masaru Moriwaki, Yoshinao Harada, Shinji Fujii, Koji Eriguchi	Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
24	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	Defect Aware to Power Conscious Tests - The New DFT Landscape.	VLSI Design	2009	DBLP DOI BibTeX RDF
20	Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta	Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Mohammad Salim Wani, Hend I. Alkhammash, M. Shiblee, Sajad A. Loan	Design and Simulation of Dual-Metal-Gate Tunnel Field Effect Transistor with Biomolecule Sensing Applications.	ICM	2023	DBLP DOI BibTeX RDF
19	Bruna Cardoso Paz, Victor El-Homsy, David J. Niegemann, Bernhard Klemt, Emmanuel Chanrion, Vivien Thiney, Baptiste Jadot, Pierre-André Mortemousque, Benoit Bertrand, Thomas Bedecarrats, Heimanu Niebojewski, François Perruchot, Silvano De Franceschi, Maud Vinet, Matias Urdampilleta, Tristan Meunier	Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology.	ESSCIRC	2022	DBLP DOI BibTeX RDF
19	Khalil Tamersit, Hocine Bourouba, Abdellah Kouzou	Improving the Current Ratio and Ambipolar Behavior of Junctionless CNTFETs Using Graded Metal Gate Work Function: A Quantum Simulation.	SSD	2022	DBLP DOI BibTeX RDF
19	Marcel A. Kossel, Vishal Khatri, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Serdar A. Yonar, Mridula Prathapan, Eric J. Lukes, Raymond A. Richetta, Carrie Cox	An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS.	ISSCC	2021	DBLP DOI BibTeX RDF
19	Shaun Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, Philex Fan, Chia-En Huang, Yu-Der Chih, Yih Wang, Jonathan Chang	A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
19	Jing-Chyi Liao, Paul Ko, M. H. Hsieh, Zheng Zeng	Self-healing LDMOSFET for high-voltage application on high-k/metal gate CMOS process.	IRPS	2020	DBLP DOI BibTeX RDF
19	Tianyu Yu, Liang Dai, Zhifeng Zhao, Weifeng Lyu, Mi Lin	Study of Work-Function Variation on Performance of Dual-Metal Gate Fin Field-Effect Transistor.	MLIS	2020	DBLP DOI BibTeX RDF
19	Cuiqin Xu, Xuejiao Wang, Wei Liu	Threshold Voltage Tuning Of 22 nm FD-SOI Devices Fabricated With Metal Gate Last Process.	ICICDT	2019	DBLP DOI BibTeX RDF
19	D. S. Huang, J. H. Lee, Y. S. Tsai, Y. F. Wang, Y. S. Huang, C. K. Lin, Ryan Lu, Jun He	Comprehensive device and product level reliability studies on advanced CMOS technologies featuring 7nm high-k metal gate FinFET transistors.	IRPS	2018	DBLP DOI BibTeX RDF
19	Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang	0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process.	SoCC	2018	DBLP DOI BibTeX RDF
19	Junrui Zhang, Francesco Bellando, Maneesha Rupakula, Erick Garcia Cordero, N. Ebejer, J. Longo, Fabien Wildhaber, Hoel Guerin, Adrian Mihai Ionescu	CMOS 3D-Extended Metal Gate ISFETs with Near Nernstian Ion Sensitivity.	DRC	2018	DBLP DOI BibTeX RDF
19	Jeffrey A. Smith, Hideki Takeuchi, Robert Stephenson, Yi-Ann Chen, Marek Hytha, Robert J. Mears, Suman Datta	Experimental Investigation of N-Channel Oxygen-Inserted (OI) Silicon Channel MOSFETs with High-K/Metal Gate Stack.	DRC	2018	DBLP DOI BibTeX RDF
19	Deepa Anand, M. Swathi, A. Purushothaman, Sundararaman Gopalan	Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate.	ICACDS (1)	2018	DBLP DOI BibTeX RDF
19	Shimpei Yamaguchi, Zeynel Bayindir, Xiaoli He, Suresh Uppal, Purushothaman Srinivasan, Chloe Yong, Dongil Choi, Manoj Joshi, Hyuck Soo Yang, Owen Hu, Srikanth Samavedam, Dong Kyun Sohn	Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
19	Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu	12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.	ISSCC	2017	DBLP DOI BibTeX RDF
19	D. H. Triyoso, G. R. Mulfinger, K. Hempel, H. Tao, F. Koehler, L. Kang, A. Kumar, T. McArdle, J. Holt, A. L. Child, S. Straub, F. Ludwig, Z. Chen, J. Kluth, Rick Carter	Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor.	ICICDT	2017	DBLP DOI BibTeX RDF
19	Tillmann Krauss, Frank Wessely, Udo Schwalke	Fabrication and simulation of electrically reconfigurable dual metal-gate planar field-effect transistors for dopant-free CMOS.	DTIS	2017	DBLP DOI BibTeX RDF
19	Andreas Kerber	Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
19	Francesco Maria Puglisi, Felipe Costantini, Ben Kaczer, Luca Larcher, Paolo Pavan	Probing defects generation during stress in high-κ/metal gate FinFETs by random telegraph noise characterization.	ESSDERC	2016	DBLP DOI BibTeX RDF
19	Tillmann Krauss, Frank Wessely, Udo Schwalke	Electrically reconfigurable dual metal-gate planar field-effect transistor for dopant-free CMOS.	SSD	2016	DBLP DOI BibTeX RDF
19	Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang	A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
19	Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, Chris H. Kim	A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
19	Shraddha Kothari, Chandan Joishi, Dhirendra Vaidya, Hasan Nejad, Benjamin Colombeau, Swaroop Ganguly, Saurabh Lodha	Metal gate VT modulation using PLAD N2 implants for Ge p-FinFET applications.	ESSDERC	2015	DBLP DOI BibTeX RDF
19	Chandrasekharan Kothandaraman, X. Chen, Dan Moy, D. Lea, Sami Rosenblatt, Faraz Khan, Derek Leu, Toshiaki Kirihata, D. Ioannou, Giuseppe La Rosa, J. B. Johnson, Norman Robson, Subramanian S. Iyer	Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications.	IRPS	2015	DBLP DOI BibTeX RDF
19	A. Kerber	Impact of RTN on stochastic BTI degradation in scaled metal gate/high-k CMOS technologies.	IRPS	2015	DBLP DOI BibTeX RDF
19	Miaomiao Wang 0006, Zuoguang Liu, Tenko Yamashita, James H. Stathis, Chia-Yu Chen	Separation of interface states and electron trapping for hot carrier degradation in ultra-scaled replacement metal gate n-FinFET.	IRPS	2015	DBLP DOI BibTeX RDF
19	A. Bezza, M. Rafik, David Roy 0001, X. Federspiel, P. Mora, Cheikh Diouf, Vincent Huard, Gérard Ghibaudo	Physical understanding of low frequency degradation of NMOS TDDB in High-k metal gate stack-based technology. Implication on lifetime assessment.	IRPS	2015	DBLP DOI BibTeX RDF
19	Jungyul Pyo, Youngmin Shin, Hoi-Jin Lee, Sung-il Bae, Min-Su Kim, Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-Wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chunghee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Ukrae Cho, Jae Cheol Son, Sungho Park	23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor.	ISSCC	2015	DBLP DOI BibTeX RDF
19	Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean	Modeling FinFET metal gate stack resistance for 14nm node and beyond.	ICICDT	2015	DBLP DOI BibTeX RDF
19	Miao Liao, Zhenghao Gan	New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
19	Yasmin Abdul Wahab, Norhayati Soin, Sharifah Wan Muhamad Hatta	Defects evolution involving interface dispersion approaches in high-k/metal-gate deep-submicron CMOS.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
19	Alessio Spessot, Marc Aoulaiche, Moonju Cho, Jacopo Franco, Tom Schram, Romain Ritzenthaler, Ben Kaczer	Impact of Off State Stress on advanced high-K metal gate NMOSFETs.	ESSDERC	2014	DBLP DOI BibTeX RDF
19	Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang	13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.	ISSCC	2014	DBLP DOI BibTeX RDF
19	Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer	Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
19	Se-Hyun Yang, Jungyul Pyo, Youngmin Shin, Jae Cheol Son	A 1.6 GHz quad-core application processor manufactured in 32 nm high-k metal gate process for smart mobile devices.	IEEE Commun. Mag.	2013	DBLP DOI BibTeX RDF
19	Seonhaeng Lee, Cheolgyu Kim, Hyeokjin Kim, Gang-Jun Kim, Ji-Hoon Seo, Donghee Son, Bongkoo Kang	Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
19	Wen-Kuan Yeh, Po-Ying Chen, Kwang-Jow Gan, Jer-Chyi Wang, Chao-Sung Lai	The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
19	Eugenio Dentoni Litta, Per-Erik Hellström, Mikael Östling	Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs.	ESSDERC	2013	DBLP DOI BibTeX RDF
19	Wataru Mizubayashi, Koichi Fukuda, Takahiro Mori, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Shin-ichi O'Uchi, Yuki Ishikawa, Shinji Migita, Yukinori Morita, Akihito Tanabe, Junichi Tsukada, Hiromi Yamauchi, Meishoku Masahara, Hiroyuki Ota	Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes.	ESSDERC	2013	DBLP DOI BibTeX RDF
19	Min Chen 0024, Vijay Reddy, Srikanth Krishnan, Jay Ondrusek, Yu Cao 0001	ACE: A robust variability and aging sensor for high-k/metal gate SoC.	ESSDERC	2013	DBLP DOI BibTeX RDF
19	Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori	A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.	ISSCC	2013	DBLP DOI BibTeX RDF
19	Youngmin Shin, Ken Shin, Prashant Kenkare, Rajesh Kashyap, Hoi-Jin Lee, Dongjoo Seo, Brian Millar, Yohan Kwon, Ravi Iyengar, Min-Su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, Wookyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae-Cheol Son, Seung Ho Hwang	28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor.	ISSCC	2013	DBLP DOI BibTeX RDF
19	Jonathan Chang, Yen-Huei Chen, Hank Cheng, Wei-Min Chan, Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang	A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications.	ISSCC	2013	DBLP DOI BibTeX RDF
19	Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic	A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
19	Masaoud Houshmand Kaffashian, Reza Lotfi, Khalil Mafinezhad, Hamid Mahmoodi	Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
19	Se-Hyun Yang, Seogjun Lee, Jae Young Lee, Jeonglae Cho, Hoi-Jin Lee, Dongsik Cho, Junghun Heo, Sunghoon Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, Seung Ho Hwang	A 32nm high-k metal gate application processor with GHz multi-core CPU.	ISSCC	2012	DBLP DOI BibTeX RDF
19	Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, Hong-Jen Liao, Jonathan Chang	A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays.	VLSIC	2012	DBLP DOI BibTeX RDF
19	Peter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee	A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
19	Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer	Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM.	VLSIC	2012	DBLP DOI BibTeX RDF
19	Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang 0001	A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
19	Hao-I Yang, Wei Hwang, Ching-Te Chuang	Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
19	Takeshi Sasaki, Takuya Imamoto, Tetsuo Endoh	Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
19	Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Kamalesh Yadav, Devendra Giri	Performance evaluation of FD-SOI Mosfets for different metal gate work function	CoRR	2011	DBLP BibTeX RDF
19	Jiann-Shiun Yuan, Wen-Kuan Yeh, Shuyu Chen, Chia-Wei Hsu	NBTI reliability on high-k metal-gate SiGe transistor and circuit performances.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
19	Florian Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel	An analog perspective on device reliability in 32nm high-κ metal gate technology.	DDECS	2011	DBLP DOI BibTeX RDF
19	Martin M. Frank	High-k/metal gate innovations enabling continued CMOS scaling.	ESSCIRC	2011	DBLP DOI BibTeX RDF
19	S. H. Yang, J. Y. Sheu, M. K. Ieong, M. H. Chiang, T. Yamamoto, J. J. Liaw, S. S. Chang, Y. M. Lin, T. L. Hsu, J. R. Hwang, J. K. Ting, C. H. Wu, K. C. Ting, F. C. Yang, C. M. Liu, I. L. Wu, Y. M. Chen, S. J. Chent, K. S. Chen, J. Y. Cheng, M. H. Tsai, W. Chang, R. Chen, C. C. Chen, T. L. Lee, C. K. Lin, S. C. Yang, Y. M. Sheu, J. T. Tzeng, L. C. Lu, S. M. Jang, Carlos H. Diaz, Yuh-Jier Mii	28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications.	CICC	2011	DBLP DOI BibTeX RDF
19	Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens	A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements.	ISSCC	2011	DBLP DOI BibTeX RDF
19	Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang 0001, Mark Bohr	A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
19	Chia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chun-Yu Chen, Yen-Ting Chiang, Feng-Renn Juang, Chien-Ting Lin, Chieh-Ming Lai	Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
19	James H. Stathis, M. Wang, K. Zhao	Reliability of advanced high-k/metal-gate n-FET devices.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
19	Enrique Miranda 0002, Eamon O'Connor, Paul K. Hurley	Exploratory analysis of the breakdown spots spatial distribution in metal gate/high-K/III-V stacks using functional summary statistics.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
19	Florian Chouard, Michael Fulde, Doris Schmitt-Landsiedel	Reliability assessment of voltage controlled oscillators in 32nm high-κ metal gate technology.	ESSCIRC	2010	DBLP DOI BibTeX RDF